Symbol: MISC_REG_AEU_GENERAL_ATTN_5
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
5369
#define MISC_REG_AEU_GENERAL_ATTN_5 0xa014UL //ACCESS:RW DataWidth:0x1 Description: set/clr general attention 5; this will set/clr bit 99 in the aeu 128 bit vector
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
33476
#define MISC_REG_AEU_GENERAL_ATTN_5 0x008414UL //Access:RW DataWidth:0x1 // Set/clr general attention 5; this will set/clr bit 53 in AEU vector.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
29968
#define MISC_REG_AEU_GENERAL_ATTN_5 0x008414UL //Access:RW DataWidth:0x1 Set/clr general attention 5; this will set/clr bit 53 in AEU vector. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
33444
#define MISC_REG_AEU_GENERAL_ATTN_5 0x008414UL //Access:RW DataWidth:0x1 // Set/clr general attention 5; this will set/clr bit 53 in AEU vector.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
33444
#define MISC_REG_AEU_GENERAL_ATTN_5 0x008414UL //Access:RW DataWidth:0x1 // Set/clr general attention 5; this will set/clr bit 53 in AEU vector.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
33444
#define MISC_REG_AEU_GENERAL_ATTN_5 0x008414UL //Access:RW DataWidth:0x1 // Set/clr general attention 5; this will set/clr bit 53 in AEU vector.