MISC_REG_CLK_100G_MODE
#define MISC_REG_CLK_100G_MODE 0x008c10UL //Access:RW DataWidth:0x3 // Per bit; 1: clk_nw and main clk are asynchronous and sync FIFOs should be used. (clk_nw = 425 MHz); 0: clk_nw and main clk are synchronous and sync FIFOs should be bypassed in latency-critical paths. bit0 - clock mux control (Obsolete), bit1 - BRB/BTB control, bit2 - NIG control. Reset on Hard reset.
#define MISC_REG_CLK_100G_MODE 0x008c10UL //Access:RW DataWidth:0x3 Per bit; 1: clk_nw and main clk are asynchronous and sync FIFOs should be used. (clk_nw = 425 MHz); 0: clk_nw and main clk are synchronous and sync FIFOs should be bypassed in latency-critical paths. bit0 - clock mux control (Obsolete), bit1 - BRB/BTB control, bit2 - NIG control. Reset on Hard reset. Chips: BB_A0 BB_B0 K2
#define MISC_REG_CLK_100G_MODE 0x008c10UL //Access:RW DataWidth:0x3 // Per bit; 1: clk_nw and main clk are asynchronous and sync FIFOs should be used. (clk_nw = 425 MHz); 0: clk_nw and main clk are synchronous and sync FIFOs should be bypassed in latency-critical paths. bit0 - clock mux control, bit1 - BRB/BTB control, bit2 - NIG control. Reset on Hard reset.
#define MISC_REG_CLK_100G_MODE 0x008c10UL //Access:RW DataWidth:0x3 // Per bit; 1: clk_nw and main clk are asynchronous and sync FIFOs should be used. (clk_nw = 425 MHz); 0: clk_nw and main clk are synchronous and sync FIFOs should be bypassed in latency-critical paths. bit0 - clock mux control (Obsolete), bit1 - BRB/BTB control, bit2 - NIG control. Reset on Hard reset.
#define MISC_REG_CLK_100G_MODE 0x008c10UL //Access:RW DataWidth:0x3 // Per bit; 1: clk_nw and main clk are asynchronous and sync FIFOs should be used. (clk_nw = 425 MHz); 0: clk_nw and main clk are synchronous and sync FIFOs should be bypassed in latency-critical paths. bit0 - clock mux control (Obsolete), bit1 - BRB/BTB control, bit2 - NIG control. Reset on Hard reset.