MISC_REG_BLOCK_256B_EN
#define MISC_REG_BLOCK_256B_EN 0x008c14UL //Access:RW DataWidth:0x2 // This register indicates if BRTB block size is 256 byte (when programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset. [0]- BRB; [1] - BTB, PBF;
#define MISC_REG_BLOCK_256B_EN 0x008c14UL //Access:RW DataWidth:0x2 This register indicates if BRTB block size is 256 byte (when programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset. [0]- BRB; [1] - BTB, PBF; Chips: BB_A0 BB_B0 K2
#define MISC_REG_BLOCK_256B_EN 0x008c14UL //Access:RW DataWidth:0x1 // This register indicates if BRTB block size is 256 byte (when programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset.
#define MISC_REG_BLOCK_256B_EN 0x008c14UL //Access:RW DataWidth:0x2 // This register indicates if BRTB block size is 256 byte (when programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset. [0]- BRB; [1] - BTB, PBF;
#define MISC_REG_BLOCK_256B_EN 0x008c14UL //Access:RW DataWidth:0x2 // This register indicates if BRB and BTB block size is 256 byte (when programmed to 1) or 128 byte (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G and 50G modes. Reset on Hard reset. [0]- BRB; [1] - BTB, PBF;