Symbol: MISC_REG_AEU_SYS_KILL_STATUS_2
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
6034
#define MISC_REG_AEU_SYS_KILL_STATUS_2 0xa608UL //ACCESS:RW DataWidth:0x20 Description: Represent the status of the input vector to the AEU when a system kill occurred. The register is reset in por reset. Mapped as follows: [0] CSEMI Parity error; [1] CSEMI Hw interrupt; [2] PXP Parity error; [3] PXP Hw interrupt; [4] PXPpciClockClient Parity error; [5] PXPpciClockClient Hw interrupt; [6] CFC Parity error; [7] CFC Hw interrupt; [8] CDU Parity error; [9] CDU Hw interrupt; [10] DMAE Parity error; [11] DMAE Hw interrupt; [12] IGU (HC) Parity error; [13] IGU (HC) Hw interrupt; [14] MISC Parity error; [15] MISC Hw interrupt; [16] pxp_misc_mps_attn; [17] Flash event; [18] SMB event; [19] MCP attn0; [20] MCP attn1; [21] SW timers attn_1 func0; [22] SW timers attn_2 func0; [23] SW timers attn_3 func0; [24] SW timers attn_4 func0;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
33730
#define MISC_REG_AEU_SYS_KILL_STATUS_2 0x00880cUL //Access:RW DataWidth:0x20 // Third 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
30222
#define MISC_REG_AEU_SYS_KILL_STATUS_2 0x00880cUL //Access:RW DataWidth:0x20 Third 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31; Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
33698
#define MISC_REG_AEU_SYS_KILL_STATUS_2 0x00880cUL //Access:RW DataWidth:0x20 // Third 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
33698
#define MISC_REG_AEU_SYS_KILL_STATUS_2 0x00880cUL //Access:RW DataWidth:0x20 // Third 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
33698
#define MISC_REG_AEU_SYS_KILL_STATUS_2 0x00880cUL //Access:RW DataWidth:0x20 // Third 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] General attn0; [1] General attn1; [2] General attn2; [3] General attn3; [4] General attn4; [5] General attn5; [6] General attn6; [7] General attn7; [8] General attn8; [9] General attn9; [10] General attn10; [11] General attn11; [12] General attn12; [13] General attn13; [14] General attn14; [15] General attn15; [16] General attn16; [17] General attn17; [18] General attn18; [19] General attn19; [20] General attn20; [21] General attn21; [22] General attn22; [23] General attn23; [24] General attn24; [25] General attn25; [26] General attn26; [27] General attn27; [28] General attn28; [29] General attn29; [30] General attn30; [31] General attn31;