Symbol: MISC_REG_AEU_SYS_KILL_STATUS_1
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
6032
#define MISC_REG_AEU_SYS_KILL_STATUS_1 0xa604UL //ACCESS:RW DataWidth:0x20 Description: Represent the status of the input vector to the AEU when a system kill occurred. The register is reset in por reset. Mapped as follows: [0] PBF Parity error; [1] PBF Hw interrupt; [2] QM Parity error; [3] QM Hw interrupt; [4] Timers Parity error; [5] Timers Hw interrupt; [6] XSDM Parity error; [7] XSDM Hw interrupt; [8] XCM Parity error; [9] XCM Hw interrupt; [10] XSEMI Parity error; [11] XSEMI Hw interrupt; [12] DoorbellQ Parity error; [13] DoorbellQ Hw interrupt; [14] NIG Parity error; [15] NIG Hw interrupt; [16] Vaux PCI core Parity error; [17] Vaux PCI core Hw interrupt; [18] Debug Parity error; [19] Debug Hw interrupt; [20] USDM Parity error; [21] USDM Hw interrupt; [22] UCM Parity error; [23] UCM Hw interrupt; [24] USEMI Parity e
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
33729
#define MISC_REG_AEU_SYS_KILL_STATUS_1 0x008808UL //Access:RW DataWidth:0x20 // Second 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
30221
#define MISC_REG_AEU_SYS_KILL_STATUS_1 0x008808UL //Access:RW DataWidth:0x20 Second 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15; Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
33697
#define MISC_REG_AEU_SYS_KILL_STATUS_1 0x008808UL //Access:RW DataWidth:0x20 // Second 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
33697
#define MISC_REG_AEU_SYS_KILL_STATUS_1 0x008808UL //Access:RW DataWidth:0x20 // Second 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
33697
#define MISC_REG_AEU_SYS_KILL_STATUS_1 0x008808UL //Access:RW DataWidth:0x20 // Second 32b of the status of the input vector to the AEU when a system kill occurred. Mapped as follows: [0] PGLUE config_space; [1] PGLUE misc_flr; [2] PGLUE B RBC Parity error;[3] PGLUE B RBC HW interrupt; [4] pglue_misc_mctp_attn; [5] Flash event; [6] SMB event; [7] Main power interrupt; [8] SW timers #1; [9] SW timers #2; [10] SW timers #3; [11] SW timers #4; [12] SW timers #5; [13] SW timers #6; [14] SW timers #7; [15] SW timers #8; [16] PCIE glue/PXP VPD event #0; [17] PCIE glue/PXP VPD event #1; [18] PCIE glue/PXP VPD event #2; [19] PCIE glue/PXP VPD event #3; [20] PCIE glue/PXP VPD event #4; [21] PCIE glue/PXP VPD event #5; [22] PCIE glue/PXP VPD event #6; [23] PCIE glue/PXP VPD event #7; [24] PCIE glue/PXP VPD event #8; [25] PCIE glue/PXP VPD event #9; [26] PCIE glue/PXP VPD event #10; [27] PCIE glue/PXP VPD event #11; [28] PCIE glue/PXP VPD event #12; [29] PCIE glue/PXP VPD event #13; [30] PCIE glue/PXP VPD event #14; [31] PCIE glue/PXP VPD event #15;