Symbol: MISC_REG_AEU_ENABLE4_IGU_OUT_0
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
33513
#define MISC_REG_AEU_ENABLE4_IGU_OUT_0 0x0084a8UL //Access:RW DataWidth:0x20 // Fourth 32b for enabling the output for output0. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] P
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
30005
#define MISC_REG_AEU_ENABLE4_IGU_OUT_0 0x0084a8UL //Access:RW DataWidth:0x20 Fourth 32b for enabling the output for output0. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt; Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
33481
#define MISC_REG_AEU_ENABLE4_IGU_OUT_0 0x0084a8UL //Access:RW DataWidth:0x20 // Fourth 32b for enabling the output for output0. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] CNIG attn port 0; [5] CNIG attn port 1; [6] CNIG attn port 2; [7] CNIG attn port 3; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [21:18] reserved; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
33481
#define MISC_REG_AEU_ENABLE4_IGU_OUT_0 0x0084a8UL //Access:RW DataWidth:0x20 // Fourth 32b for enabling the output for output0. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
33481
#define MISC_REG_AEU_ENABLE4_IGU_OUT_0 0x0084a8UL //Access:RW DataWidth:0x20 // Fourth 32b for enabling the output for output0. Mapped as follows: [0] General attn32; [1] General attn33; [2] General attn34; [3] General attn35; [4] NWS Parity error; [5] NWS HW interrupt; [6] NWM Parity error; [7] NWM HW interrupt; [8] MCP CPU Event; [9] MCP Watchdog timer; [10] MCP M2P attn; [11] AVS Stop status ready; [12] MSTAT Parity error; [13] MSTAT HW interrupt; [14] MSTAT per-path Parity error; [15] MSTAT per-path HW interrupt; [16] OPTE Parity error; [17] MCP Parity error; [18] MS HW interrupt; [19] UMAC HW interrupt; [20] LED HW interrupt; [21] BMBN HW interrupt; [22] NIG Parity error; [23] NIG HW interrupt; [24] BMB Parity error; [25] BMB HW interrupt; [26] BTB Parity error; [27] BTB HW interrupt; [28] BRB Parity error; [29] BRB HW interrupt; [30] PRS Parity error; [31] PRS HW interrupt;