Symbol: MISC_REG_AEU_ENABLE1_IGU_OUT_0
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
33510
#define MISC_REG_AEU_ENABLE1_IGU_OUT_0 0x00849cUL //Access:RW DataWidth:0x20 // First 32b for enabling the output for output0. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
30002
#define MISC_REG_AEU_ENABLE1_IGU_OUT_0 0x00849cUL //Access:RW DataWidth:0x20 First 32b for enabling the output for output0. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31; Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
33478
#define MISC_REG_AEU_ENABLE1_IGU_OUT_0 0x00849cUL //Access:RW DataWidth:0x20 // First 32b for enabling the output for output0. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
33478
#define MISC_REG_AEU_ENABLE1_IGU_OUT_0 0x00849cUL //Access:RW DataWidth:0x20 // First 32b for enabling the output for output0. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
33478
#define MISC_REG_AEU_ENABLE1_IGU_OUT_0 0x00849cUL //Access:RW DataWidth:0x20 // First 32b for enabling the output for output0. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;