Symbol: MISC_REG_AEU_AFTER_INVERT_1_MCP
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
5910
#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0xa434UL //ACCESS:R DataWidth:0x20 Description: read first 32 bit after inversion of mcp. mapped as follows: [0] NIG attention for function0; [1] NIG attention for function1; [2] GPIO1 mcp; [3] GPIO2 mcp; [4] GPIO3 mcp; [5] GPIO4 mcp; [6] GPIO1 function 1; [7] GPIO2 function 1; [8] GPIO3 function 1; [9] GPIO4 function 1; [10] PCIE glue/PXP VPD event function0; [11] PCIE glue/PXP VPD event function1; [12] PCIE glue/PXP Expansion ROM event0; [13] PCIE glue/PXP Expansion ROM event1; [14] SPIO4; [15] SPIO5; [16] MSI/X indication for mcp; [17] MSI/X indication for function 1; [18] BRB Parity error; [19] BRB Hw interrupt; [20] PRS Parity error; [21] PRS Hw interrupt; [22] SRC Parity error; [23] SRC Hw interrupt; [24] TSDM Parity error; [25] TSDM Hw interrupt; [26] TCM Parity error; [27] T
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
33717
#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0x0087d8UL //Access:R DataWidth:0x20 // First 32b read after invert of input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
30209
#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0x0087d8UL //Access:R DataWidth:0x20 First 32b read after invert of input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31; Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
33685
#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0x0087d8UL //Access:R DataWidth:0x20 // First 32b read after invert of input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
33685
#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0x0087d8UL //Access:R DataWidth:0x20 // First 32b read after invert of input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
33685
#define MISC_REG_AEU_AFTER_INVERT_1_MCP 0x0087d8UL //Access:R DataWidth:0x20 // First 32b read after invert of input. Mapped as follows: [0] GPIO0; [1] GPIO1; [2] GPIO2; [3] GPIO3; [4] GPIO4; [5] GPIO5; [6] GPIO6; [7] GPIO; [8] GPIO8; [9] GPIO9; [10] GPIO10; [11] GPIO11; [12] GPIO12; [13] GPIO13; [14] GPIO14; [15] GPIO15; [16] GPIO16; [17] GPIO17; [18] GPIO18; [19] GPIO19; [20] GPIO20; [21] GPIO21; [22] GPIO22; [23] GPIO23; [24] GPIO24; [25] GPIO25; [26] GPIO26; [27] GPIO27; [28] GPIO28; [29] GPIO29; [30] GPIO30; [31] GPIO31;