MISCS_REG_RESET_PL_HV_2
#define MISCS_REG_RESET_PL_HV_2 0x009150UL //Access:RW DataWidth:0x20 Reset_reg: Shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nwm; [1] rst_nwm_mac0; [2] rst_nwm_mac1; [3] rst_nwm_mac2; [4] rst_nwm_mac3; [5] rst_nwm_gpcs0; [6] rst_nwm_gpcs1; [7] rst_nwm_gpcs2; [8] rst_nwm_gpcs3; [9] rst_nwm_xpcs0; [10] rst_nwm_xpcs1; [11] rst_nwm_xpcs2; [12
#define MISCS_REG_RESET_PL_HV_2 0x009150UL //Access:RW DataWidth:0x20 // Reset_reg: Shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nwm; [1] rst_nwm_mac0; [2] rst_nwm_mac1; [3] rst_nwm_mac2; [4] rst_nwm_mac3; [5] rst_nwm_gpcs0; [6] rst_nwm_gpcs1; [7] rst_nwm_gpcs2; [8] rst_nwm_gpcs3; [9] rst_nwm_xpcs0; [10] rst_nwm_xpcs1; [11] rst_nwm_xpcs2; [12] rst_nwm_xpcs3; [13] rst_nwm_xpcs4; [14] rst_nwm_xpcs5; [15] rst_nwm_xpcs6; [16] rst_nwm_xpcs7; [17] rst_nwm_tx_lane0; [18] rst_nwm_tx_lane1; [19] rst_nwm_tx_lane2; [20] rst_nwm_tx_lane3; [21] rst_nwm_rx_lane0; [22] rst_nwm_rx_lane1; [23] rst_nwm_rx_lane2; [24] rst_nwm_rx_lane3; [25] rst_nwm_sdgb; [31:26] reserved; Global register.
#define MISCS_REG_RESET_PL_HV_2 0x009150UL //Access:RW DataWidth:0x20 // Reset_reg: Shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nwm; [1] rst_nwm_mac0; [2] rst_nwm_mac1; [3] rst_nwm_mac2; [4] rst_nwm_mac3; [5] rst_nwm_gpcs0; [6] rst_nwm_gpcs1; [7] rst_nwm_gpcs2; [8] rst_nwm_gpcs3; [9] rst_nwm_xpcs0; [10] rst_nwm_xpcs1; [11] rst_nwm_xpcs2; [12] rst_nwm_xpcs3; [13] rst_nwm_xpcs4; [14] rst_nwm_xpcs5; [15] rst_nwm_xpcs6; [16] rst_nwm_xpcs7; [17] rst_nwm_tx_lane0; [18] rst_nwm_tx_lane1; [19] rst_nwm_tx_lane2; [20] rst_nwm_tx_lane3; [21] rst_nwm_rx_lane0; [22] rst_nwm_rx_lane1; [23] rst_nwm_rx_lane2; [24] rst_nwm_rx_lane3; [25] rst_nwm_sdgb; [31:26] reserved; Global register.
#define MISCS_REG_RESET_PL_HV_2 0x009150UL //Access:RW DataWidth:0x20 // Reset_reg: Shared blocks which are reset only by the MCP (PL=UA); Read: read one = the specific block is out of reset; read zero = the specific block is in reset; Write: addr0 ("wr"): writing "0" resets the corresponding block, writing "1" takes a block out of reset. addr1 ("set"): writing "0" doesn't change the reset state of the corresponding block, writing "1" takes a block out of reset. addr2 ("clear"): writing "0" doesn't change the reset state of the corresponding block, writing "1" resets the block. addr 3-ignore; The order of the bits is: [0] rst_nwm; [1] rst_nwm_mac0; [2] rst_nwm_mac1; [3] rst_nwm_mac2; [4] rst_nwm_mac3; [5] rst_nwm_gpcs0; [6] rst_nwm_gpcs1; [7] rst_nwm_gpcs2; [8] rst_nwm_gpcs3; [9] rst_nwm_xpcs0; [10] rst_nwm_xpcs1; [11] rst_nwm_xpcs2; [12] rst_nwm_xpcs3; [13] rst_nwm_xpcs4; [14] rst_nwm_xpcs5; [15] rst_nwm_xpcs6; [16] rst_nwm_xpcs7; [17] rst_nwm_tx_lane0; [18] rst_nwm_tx_lane1; [19] rst_nwm_tx_lane2; [20] rst_nwm_tx_lane3; [21] rst_nwm_rx_lane0; [22] rst_nwm_rx_lane1; [23] rst_nwm_rx_lane2; [24] rst_nwm_rx_lane3; [25] rst_nwm_sdgb; [31:26] reserved; Global register.