MISCS_REG_PLL_MAIN_CTRL_4
#define MISCS_REG_PLL_MAIN_CTRL_4 0x00974cUL //Access:RW DataWidth:0x2 // Bit0 = Controls the glitch-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bit 1 in this regitser); reset (to 0) with hard_rst_b. bit1 =Glichless mux manual setting has affect when bit 0 = 1: 0-select USPLL clock; 1-select 25Mhz (ref clock); Reset (to 0) with hard_rst_b. Reset on POR reset.
#define MISCS_REG_PLL_MAIN_CTRL_4 0x00974cUL //Access:RW DataWidth:0x2 Bit0 = Controls the glitch-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bit 1 in this regitser); reset (to 0) with hard_rst_b. bit1 =Glichless mux manual setting has affect when bit 0 = 1: 0-select USPLL clock; 1-select 25Mhz (ref clock); Reset (to 0) with hard_rst_b. Reset on POR reset. Chips: BB_A0 BB_B0 K2
#define MISCS_REG_PLL_MAIN_CTRL_4 0x00974cUL //Access:RW DataWidth:0x2 // Bit0 = Controls the glitch-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bit 1 in this regitser); reset (to 0) with hard_rst_b. bit1 =Glichless mux manual setting has affect when bit 0 = 1: 0-select USPLL clock; 1-select 25Mhz (ref clock); Reset (to 0) with hard_rst_b. Reset on POR reset.
#define MISCS_REG_PLL_MAIN_CTRL_4 0x00974cUL //Access:RW DataWidth:0x2 // Bit0 = Controls the glitch-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bit 1 in this regitser); reset (to 0) with hard_rst_b. bit1 =Glichless mux manual setting has affect when bit 0 = 1: 0-select USPLL clock; 1-select 25Mhz (ref clock); Reset (to 0) with hard_rst_b. Reset on POR reset.
#define MISCS_REG_PLL_MAIN_CTRL_4 0x00974cUL //Access:RW DataWidth:0x2 // Bit0 = Controls the glitch-less mux control source: 0-management power sequencer output; 1-glich-less mux manual setting (bit 1 in this regitser); reset (to 0) with hard_rst_b. bit1 =Glichless mux manual setting has affect when bit 0 = 1: 0-select USPLL clock; 1-select 25Mhz (ref clock); Reset (to 0) with hard_rst_b. Reset on POR reset.