Symbol: MISCS_REG_GENERIC_POR_0
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
34148
#define MISCS_REG_GENERIC_POR_0 0x0096d4UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by por reset. bit 0 is used for Vmain state machine system kill reset. If clear will not reset all the Vmain sm (backward compatible); if set will reset all the Vmain state machine. Reset on POR reset.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
30640
#define MISCS_REG_GENERIC_POR_0 0x0096d4UL //Access:RW DataWidth:0x20 Debug only: spare RW register reset by por reset. bit 0 is used for Vmain state machine system kill reset. If clear will not reset all the Vmain sm (backward compatible); if set will reset all the Vmain state machine. Reset on POR reset. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
34116
#define MISCS_REG_GENERIC_POR_0 0x0096d4UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by por reset. bit 0 is used for Vmain state machine system kill reset. If clear will not reset all the Vmain sm (backward compatible); if set will reset all the Vmain state machine. Reset on POR reset.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
34116
#define MISCS_REG_GENERIC_POR_0 0x0096d4UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by por reset. bit 0 is used for Vmain state machine system kill reset. If clear will not reset all the Vmain sm (backward compatible); if set will reset all the Vmain state machine. Reset on POR reset.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
34116
#define MISCS_REG_GENERIC_POR_0 0x0096d4UL //Access:RW DataWidth:0x20 // Debug only: spare RW register reset by por reset. bit 0 is used for Vmain state machine system kill reset. If clear will not reset all the Vmain sm (backward compatible); if set will reset all the Vmain state machine. Reset on POR reset.