MISCS_REG_DRIVER_CONTROL_0
#define MISCS_REG_DRIVER_CONTROL_0 0x009088UL //Access:RW DataWidth:0x20 // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT
#define MISCS_REG_DRIVER_CONTROL_0 0x009088UL //Access:RW DataWidth:0x20 These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. Chips: BB_A0 BB_B0 K2
#define MISCS_REG_DRIVER_CONTROL_0 0x009088UL //Access:RW DataWidth:0x20 // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
#define MISCS_REG_DRIVER_CONTROL_0 0x009088UL //Access:RW DataWidth:0x20 // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.
#define MISCS_REG_DRIVER_CONTROL_0 0x009088UL //Access:RW DataWidth:0x20 // These registers represent 16 per-path clients and 32 resources. Each resource can be controlled by one client only. One in each bit represent that this client controls the appropriate resource (Ex: bit 5 set means this client controls resource number 5). Write: addr1 = set "request"; addr0 = clear both "grant" and "request"; Read: addr1 = read "request" status; addr0 = read "grant" status; Write to address 1 will set a "request" to control all the resources which appropriate bit (in the write command) is set. If the resource is free (no "request" and no "grant"), one will be written to that client "request" register to corresponding resource bit. If the requested resource is already set in the given client "request" register or "grant" register the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted. All the requests for given resource participate in round-robin arbitration. Write to address 0 will write zero to this client "grant" and "request" register to all the resources which appropriate bit (in the write command) is set. If the appropriate bit is clear (no "request" and no "grant") the MISC_REGISTERS_INT_STS.GENERIC_SW interrupt will be asserted.