MISCS_REG_CMT_ENABLED_FOR_PAIR
#define MISCS_REG_CMT_ENABLED_FOR_PAIR 0x00971cUL //Access:RW DataWidth:0x8 // For Coupled Mode Teaming. Each bit corresponds to a PF pair i.e. bit 0 for global PFs 0 and 1; bit 1 for global PFs 2 and 3. If the bit is clear then the PFs for that pair are not coupled and the even PF is mapped to path 0 and the odd PF is mapped to path 1. This is the same mapping E2 and E3 have. If the bit is set then those PFs are coupled. In this case the even PF is mapped to both paths and the odd PF is disabled.
#define MISCS_REG_CMT_ENABLED_FOR_PAIR 0x00971cUL //Access:RW DataWidth:0x8 For Coupled Mode Teaming. Each bit corresponds to a PF pair i.e. bit 0 for global PFs 0 and 1; bit 1 for global PFs 2 and 3. If the bit is clear then the PFs for that pair are not coupled and the even PF is mapped to path 0 and the odd PF is mapped to path 1. This is the same mapping E2 and E3 have. If the bit is set then those PFs are coupled. In this case the even PF is mapped to both paths and the odd PF is disabled. Chips: BB_A0 BB_B0 K2
#define MISCS_REG_CMT_ENABLED_FOR_PAIR 0x00971cUL //Access:RW DataWidth:0x8 // For Coupled Mode Teaming. Each bit corresponds to a PF pair i.e. bit 0 for global PFs 0 and 1; bit 1 for global PFs 2 and 3. If the bit is clear then the PFs for that pair are not coupled and the even PF is mapped to path 0 and the odd PF is mapped to path 1. This is the same mapping E2 and E3 have. If the bit is set then those PFs are coupled. In this case the even PF is mapped to both paths and the odd PF is disabled.
#define MISCS_REG_CMT_ENABLED_FOR_PAIR 0x00971cUL //Access:RW DataWidth:0x8 // For Coupled Mode Teaming. Each bit corresponds to a PF pair i.e. bit 0 for global PFs 0 and 1; bit 1 for global PFs 2 and 3. If the bit is clear then the PFs for that pair are not coupled and the even PF is mapped to path 0 and the odd PF is mapped to path 1. This is the same mapping E2 and E3 have. If the bit is set then those PFs are coupled. In this case the even PF is mapped to both paths and the odd PF is disabled.
#define MISCS_REG_CMT_ENABLED_FOR_PAIR 0x00971cUL //Access:RW DataWidth:0x8 // For Coupled Mode Teaming. Each bit corresponds to a PF pair i.e. bit 0 for global PFs 0 and 1; bit 1 for global PFs 2 and 3. If the bit is clear then the PFs for that pair are not coupled and the even PF is mapped to path 0 and the odd PF is mapped to path 1. This is the same mapping E2 and E3 have. If the bit is set then those PFs are coupled. In this case the even PF is mapped to both paths and the odd PF is disabled.