MISCS_REG_CLK_100G_MODE
#define MISCS_REG_CLK_100G_MODE 0x009070UL //Access:RW DataWidth:0x1 // This register indicates if clk_nw frequency is faster than main clock frequency (when programmed to 1) or is the same as main clock frequency (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G mode. In AH it control SYNC FIFOs in the BMB.
#define MISCS_REG_CLK_100G_MODE 0x009070UL //Access:RW DataWidth:0x1 This register indicates if clk_nw frequency is faster than main clock frequency (when programmed to 1) or is the same as main clock frequency (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G mode. In AH it control SYNC FIFOs in the BMB. Chips: BB_A0 BB_B0 K2
#define MISCS_REG_CLK_100G_MODE 0x009070UL //Access:RW DataWidth:0x3 // This register indicates if clk_nw frequency is faster than main clock frequency (when programmed to 1) or is the same as main clock frequency (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G mode. bit0 - RBC control, bit1 - BMB control. bit2 - clock mux control. Reset on Hard reset.
#define MISCS_REG_CLK_100G_MODE 0x009070UL //Access:RW DataWidth:0x1 // This register indicates if clk_nw frequency is faster than main clock frequency (when programmed to 1) or is the same as main clock frequency (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G mode. In AH it control SYNC FIFOs in the BMB.
#define MISCS_REG_CLK_100G_MODE 0x009070UL //Access:RW DataWidth:0x1 // This register indicates if clk_nw frequency is faster than main clock frequency (when programmed to 1) or is the same as main clock frequency (when programmed to 0). In E4 (BigBear) it should be set to 1 in 100G mode. In AH it control SYNC FIFOs in the BMB.