MCP_REG_CPU_PROGRAM_COUNTER
#define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL //Access:RW DataWidth:0x20 // This register allows the program counter to read at any time. The value can be modified when the processor is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. '1's written to bits 1-0 are ignored. If the processor has a ROM, then the reset value of this register points to the internal ROM. If the processor does not have a ROM, then this reset value points to the scratchpad area.
#define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL //Access:RW DataWidth:0x20 This register allows the program counter to read at any time. The value can be modified when the processor is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. '1's written to bits 1-0 are ignored. If the processor has a ROM, then the reset value of this register points to the internal ROM. If the processor does not have a ROM, then this reset value points to the scratchpad area. Chips: BB_A0 BB_B0 K2
#define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL //Access:RW DataWidth:0x20 // This register allows the program counter to read at any time. The value can be modified when the processor is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. '1's written to bits 1-0 are ignored. If the processor has a ROM, then the reset value of this register points to the internal ROM. If the processor does not have a ROM, then this reset value points to the scratchpad area.
#define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL //Access:RW DataWidth:0x20 // This register allows the program counter to read at any time. The value can be modified when the processor is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. '1's written to bits 1-0 are ignored. If the processor has a ROM, then the reset value of this register points to the internal ROM. If the processor does not have a ROM, then this reset value points to the scratchpad area.
#define MCP_REG_CPU_PROGRAM_COUNTER 0xe0501cUL //Access:RW DataWidth:0x20 // This register allows the program counter to read at any time. The value can be modified when the processor is halted. Writes will also clear any pending instruction in the decode stage of the pipeline. Bits 31-2 are implemented. '1's written to bits 1-0 are ignored. If the processor has a ROM, then the reset value of this register points to the internal ROM. If the processor does not have a ROM, then this reset value points to the scratchpad area.