Symbol: IGU_REG_VF_CONFIGURATION
usr/src/uts/common/io/bnxe/577xx/hsi/hw/include/57712_reg.h
5326
#define IGU_REG_VF_CONFIGURATION 0x130170UL //ACCESS:RW DataWidth:0x8 SPLIT:64 Description: d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enable; d7:d5 parent PF
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
38486
#define IGU_REG_VF_CONFIGURATION 0x180804UL //Access:RW DataWidth:0x9 // d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enable; d8:d5 parent PF (BB supports only 0-7 PF).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
34823
#define IGU_REG_VF_CONFIGURATION 0x180804UL //Access:RW DataWidth:0x9 d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enable; d8:d5 parent PF (BB supports only 0-7 PF). Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
38040
#define IGU_REG_VF_CONFIGURATION 0x180804UL //Access:RW DataWidth:0x9 // d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enable; d8:d5 parent PF (BB supports only 0-7 PF).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
38040
#define IGU_REG_VF_CONFIGURATION 0x180804UL //Access:RW DataWidth:0x9 // d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enable; d8:d5 parent PF (BB supports only 0-7 PF).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
38040
#define IGU_REG_VF_CONFIGURATION 0x180804UL //Access:RW DataWidth:0x9 // d0 - function enable; d1 - MSI/MSIX enable; d3:d2 reserved; d4 - single ISR mode enable; d8:d5 parent PF (BB supports only 0-7 PF).