IGU_REG_TRAILING_EDGE_LATCH
#define IGU_REG_TRAILING_EDGE_LATCH 0x130104UL //ACCESS:RW DataWidth:0x10 SPLIT:8 Description: Attention signals trailing edge. attn bit condition monitoring; each bit that is set will lock a change from 1 to 0 in the corresponding attention signals that comes from the AEU
#define IGU_REG_TRAILING_EDGE_LATCH 0x180830UL //Access:RW DataWidth:0x20 // Attention signals trailing edge. attn bit condition monitoring; each bit that is set will lock a change from 1 to 0 in the corresponding attention signals that comes from the AEU.
#define IGU_REG_TRAILING_EDGE_LATCH 0x180830UL //Access:RW DataWidth:0x20 Attention signals trailing edge. attn bit condition monitoring; each bit that is set will lock a change from 1 to 0 in the corresponding attention signals that comes from the AEU. Chips: BB_A0 BB_B0 K2
#define IGU_REG_TRAILING_EDGE_LATCH 0x180830UL //Access:RW DataWidth:0x20 // Attention signals trailing edge. attn bit condition monitoring; each bit that is set will lock a change from 1 to 0 in the corresponding attention signals that comes from the AEU.
#define IGU_REG_TRAILING_EDGE_LATCH 0x180830UL //Access:RW DataWidth:0x20 // Attention signals trailing edge. attn bit condition monitoring; each bit that is set will lock a change from 1 to 0 in the corresponding attention signals that comes from the AEU.
#define IGU_REG_TRAILING_EDGE_LATCH 0x180830UL //Access:RW DataWidth:0x20 // Attention signals trailing edge. attn bit condition monitoring; each bit that is set will lock a change from 1 to 0 in the corresponding attention signals that comes from the AEU.