IGU_REG_RESET_MEMORIES
#define IGU_REG_RESET_MEMORIES 0x130158UL //ACCESS:RW DataWidth:0x6 Description: Write one for each bit will reset the appropriate memory. When the memory reset finished the appropriate bit will be clear. Bit 0 - mapping memory; Bit 1 - SB memory; Bit 2 - SB interrupt and mask register; Bit 3 - MSIX memory; Bit 4 - PBA memory; Bit 5 - statistics;
#define IGU_REG_RESET_MEMORIES 0x180000UL //Access:RW DataWidth:0x7 // Write one for each bit resets the appropriate memory. When the memory reset finished the appropriate bit is cleared. Bit 0 - mapping memory; Bit 1 - SB memory (producer and consumer); Bit 2 - SB interrupt before mask and mask memories; Bit 3 - MSIX memory; Bit 4 - PBA memory; Bit 5 - number of messages sent statistics; Bit 6 - RL memories (variable 0, variable 1 and statistics).
#define IGU_REG_RESET_MEMORIES 0x180000UL //Access:RW DataWidth:0x7 Write one for each bit resets the appropriate memory. When the memory reset finished the appropriate bit is cleared. Bit 0 - mapping memory; Bit 1 - SB memory (producer and consumer); Bit 2 - SB interrupt before mask and mask memories; Bit 3 - MSIX memory; Bit 4 - PBA memory; Bit 5 - number of messages sent statistics; Bit 6 - RL memories (variable 0, variable 1 and statistics). Chips: BB_A0 BB_B0 K2
#define IGU_REG_RESET_MEMORIES 0x180000UL //Access:RW DataWidth:0x7 // Write one for each bit resets the appropriate memory. When the memory reset finished the appropriate bit is cleared. Bit 0 - mapping memory; Bit 1 - SB memory (producer and consumer); Bit 2 - SB interrupt before mask and mask memories; Bit 3 - MSIX memory; Bit 4 - PBA memory; Bit 5 - number of messages sent statistics; Bit 6 - RL memories (variable 0, variable 1 and statistics).
#define IGU_REG_RESET_MEMORIES 0x180000UL //Access:RW DataWidth:0x7 // Write one for each bit resets the appropriate memory. When the memory reset finished the appropriate bit is cleared. Bit 0 - mapping memory; Bit 1 - SB memory (producer and consumer); Bit 2 - SB interrupt before mask and mask memories; Bit 3 - MSIX memory; Bit 4 - PBA memory; Bit 5 - number of messages sent statistics; Bit 6 - RL memories (variable 0, variable 1 and statistics).
#define IGU_REG_RESET_MEMORIES 0x180000UL //Access:RW DataWidth:0x7 // Write one for each bit resets the appropriate memory. When the memory reset finished the appropriate bit is cleared. Bit 0 - mapping memory; Bit 1 - SB memory (producer and consumer); Bit 2 - SB interrupt before mask and mask memories; Bit 3 - MSIX memory; Bit 4 - PBA memory; Bit 5 - number of messages sent statistics; Bit 6 - RL memories (variable 0, variable 1 and statistics).