IGU_REG_LEADING_EDGE_LATCH
#define IGU_REG_LEADING_EDGE_LATCH 0x130134UL //ACCESS:RW DataWidth:0x10 SPLIT:8 Description: Attention signals leading edge. attn bit condition monitoring; each bit that is set will lock a change from 0 to 1 in the corresponding attention signals that comes from the AEU
#define IGU_REG_LEADING_EDGE_LATCH 0x18082cUL //Access:RW DataWidth:0x20 // Attention signals leading edge. attn bit condition monitoring; each bit that is set will lock a change from 0 to 1 in the corresponding attention signals that comes from the AEU.
#define IGU_REG_LEADING_EDGE_LATCH 0x18082cUL //Access:RW DataWidth:0x20 Attention signals leading edge. attn bit condition monitoring; each bit that is set will lock a change from 0 to 1 in the corresponding attention signals that comes from the AEU. Chips: BB_A0 BB_B0 K2
#define IGU_REG_LEADING_EDGE_LATCH 0x18082cUL //Access:RW DataWidth:0x20 // Attention signals leading edge. attn bit condition monitoring; each bit that is set will lock a change from 0 to 1 in the corresponding attention signals that comes from the AEU.
#define IGU_REG_LEADING_EDGE_LATCH 0x18082cUL //Access:RW DataWidth:0x20 // Attention signals leading edge. attn bit condition monitoring; each bit that is set will lock a change from 0 to 1 in the corresponding attention signals that comes from the AEU.
#define IGU_REG_LEADING_EDGE_LATCH 0x18082cUL //Access:RW DataWidth:0x20 // Attention signals leading edge. attn bit condition monitoring; each bit that is set will lock a change from 0 to 1 in the corresponding attention signals that comes from the AEU.