IGU_REG_COMMAND_REG_CTRL
#define IGU_REG_COMMAND_REG_CTRL 0x13012cUL //ACCESS:W DataWidth:0x15 SPLIT:8 Description: [11:0] - PXP BAR address; [18:12] - FID (if VF - [18] = 0; [17:12] = VF number; if PF - [18] = 1; [17:15] = 0; [14:12] = PFID); [19] - reserved; [20] command type - 0-read; 1-wr. When writing to this register the command will be executed. On write command the 32 LSB command should be written first (to the command_reg_32lsb_data register) and only then this register. PXP BAR address field: 0x000 - 0x1FF - reserved; 0x200 - PBA ; 0x201 - 0x3FF - reserved; 0x400 - 0x487 - interrupt ack register; 0x488-0x4FF - reserved; 0x500 - 0x587 - producer update; 0x588-0x59F - reserved; 0x5A0 - Attention bits update register; 0x5A1 - Attention bits set register; 0x5A2 - Attention bits clear register; 0x5A3 - SIMD with mask 64b; 0x5A4 - SIMD wi
#define IGU_REG_COMMAND_REG_CTRL 0x180848UL //Access:W DataWidth:0x20 // [15:0] - function number: opaque fid. [28:16] - PXP BAR address; [30:29] - Reserved; [31] command type - 0-read; 1-wr. When writing to this register the command will be executed. On write command the 32 LSB command should be written first (to the command_reg_32lsb_data register) and only then this register. PXP BAR address field: same as IGU BAR mapping. The following addresses are write only: interrupt ack register; producer update; Attention bits update register; Attention bits set register; Attention bits clear register. The following addresses are read only: PBA; SIMD with mask 64b; SIMD with mask 32 LSB; SIMD with mask 32 MSB; SIMD without mask 64b. The read data is copied to command_reg_32lsb_data and command_reg_32msb_data registers. On read from reserved addresses the read data will be 0.
#define IGU_REG_COMMAND_REG_CTRL 0x180848UL //Access:W DataWidth:0x20 [15:0] - function number: opaque fid. [27:16] - PXP BAR address; [30:28] - Reserved; [31] command type - 0-read; 1-wr. When writing to this register the command will be executed. On write command the 32 LSB command should be written first (to the command_reg_32lsb_data register) and only then this register. PXP BAR address field: same as IGU BAR mapping. The following addresses are write only: interrupt ack register; producer update; Attention bits update register; Attention bits set register; Attention bits clear register. The following addresses are read only: PBA; SIMD with mask 64b; SIMD with mask 32 LSB; SIMD with mask 32 MSB; SIMD without mask 64b. The read data is copied to command_reg_32lsb_data and command_reg_32msb_data registers. On read from reserved addresses the read data will be 0. Chips: BB_A0 BB_B0 K2
#define IGU_REG_COMMAND_REG_CTRL 0x180848UL //Access:W DataWidth:0x20 // [15:0] - function number: opaque fid. [27:16] - PXP BAR address; [30:28] - Reserved; [31] command type - 0-read; 1-wr. When writing to this register the command will be executed. On write command the 32 LSB command should be written first (to the command_reg_32lsb_data register) and only then this register. PXP BAR address field: same as IGU BAR mapping. The following addresses are write only: interrupt ack register; producer update; Attention bits update register; Attention bits set register; Attention bits clear register. The following addresses are read only: PBA; SIMD with mask 64b; SIMD with mask 32 LSB; SIMD with mask 32 MSB; SIMD without mask 64b. The read data is copied to command_reg_32lsb_data and command_reg_32msb_data registers. On read from reserved addresses the read data will be 0.
#define IGU_REG_COMMAND_REG_CTRL 0x180848UL //Access:W DataWidth:0x20 // [15:0] - function number: opaque fid. [27:16] - PXP BAR address; [30:28] - Reserved; [31] command type - 0-read; 1-wr. When writing to this register the command will be executed. On write command the 32 LSB command should be written first (to the command_reg_32lsb_data register) and only then this register. PXP BAR address field: same as IGU BAR mapping. The following addresses are write only: interrupt ack register; producer update; Attention bits update register; Attention bits set register; Attention bits clear register. The following addresses are read only: PBA; SIMD with mask 64b; SIMD with mask 32 LSB; SIMD with mask 32 MSB; SIMD without mask 64b. The read data is copied to command_reg_32lsb_data and command_reg_32msb_data registers. On read from reserved addresses the read data will be 0.
#define IGU_REG_COMMAND_REG_CTRL 0x180848UL //Access:W DataWidth:0x20 // [15:0] - function number: opaque fid. [27:16] - PXP BAR address; [30:28] - Reserved; [31] command type - 0-read; 1-wr. When writing to this register the command will be executed. On write command the 32 LSB command should be written first (to the command_reg_32lsb_data register) and only then this register. PXP BAR address field: same as IGU BAR mapping. The following addresses are write only: interrupt ack register; producer update; Attention bits update register; Attention bits set register; Attention bits clear register. The following addresses are read only: PBA; SIMD with mask 64b; SIMD with mask 32 LSB; SIMD with mask 32 MSB; SIMD without mask 64b. The read data is copied to command_reg_32lsb_data and command_reg_32msb_data registers. On read from reserved addresses the read data will be 0.