IGU_REG_COMMAND_DEBUG
#define IGU_REG_COMMAND_DEBUG 0x130034UL //ACCESS:RW DataWidth:0x1 Description: Debug only: 0 - FIFO collects eight first error messages; 1 - FIFO collects eight last incoming command.
#define IGU_REG_COMMAND_DEBUG 0x181518UL //Access:RW DataWidth:0x1 // Debug only: 0 - FIFO collects 64 first error messages; 1 - FIFO collects 64 last incoming command.
#define IGU_REG_COMMAND_DEBUG 0x181518UL //Access:RW DataWidth:0x1 Debug only: 0 - FIFO collects 64 first error messages; 1 - FIFO collects 64 last incoming command. Chips: BB_A0 BB_B0 K2
#define IGU_REG_COMMAND_DEBUG 0x181518UL //Access:RW DataWidth:0x1 // Debug only: 0 - FIFO collects 64 first error messages; 1 - FIFO collects 64 last incoming command.
#define IGU_REG_COMMAND_DEBUG 0x181518UL //Access:RW DataWidth:0x1 // Debug only: 0 - FIFO collects 64 first error messages; 1 - FIFO collects 64 last incoming command.
#define IGU_REG_COMMAND_DEBUG 0x181518UL //Access:RW DataWidth:0x1 // Debug only: 0 - FIFO collects 64 first error messages; 1 - FIFO collects 64 last incoming command.