IGU_REG_CLEANUP_STATUS_4
#define IGU_REG_CLEANUP_STATUS_4 0x180b80UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer and consumer command. The array size is 16 rows of 32 bits each (16 * 32bits = 512 SBs).
#define IGU_REG_CLEANUP_STATUS_4 0x180b80UL //Access:R DataWidth:0x20 Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer and consumer command. In BB an array of 9 rows is applicable (9 * 32bits = 288 SBs). In K2 an array of 12 rows is applicable, in the last row only the first 16 bits are applicable (11.5 * 32bits = 368 SBs). Chips: BB_A0 BB_B0 K2
#define IGU_REG_CLEANUP_STATUS_4 0x180b80UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer and consumer command. In BB an array of 9 rows is applicable (9 * 32bits = 288 SBs). In K2 an array of 12 rows is applicable, in the last row only the first 16 bits are applicable (11.5 * 32bits = 368 SBs).
#define IGU_REG_CLEANUP_STATUS_4 0x180b80UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer and consumer command. In BB an array of 9 rows is applicable (9 * 32bits = 288 SBs). In K2 an array of 12 rows is applicable, in the last row only the first 16 bits are applicable (11.5 * 32bits = 368 SBs).
#define IGU_REG_CLEANUP_STATUS_4 0x180b80UL //Access:R DataWidth:0x20 // Cleanup bit status per SB. 1 = cleanup is set. 0 = cleanup bit is clear. The bits in this registers are set and clear via the producer and consumer command. In BB an array of 9 rows is applicable (9 * 32bits = 288 SBs). In K2 an array of 12 rows is applicable, in the last row only the first 16 bits are applicable (11.5 * 32bits = 368 SBs).