Symbol: IGU_REG_ATTENTION_ENABLE
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
38524
#define IGU_REG_ATTENTION_ENABLE 0x18083cUL //Access:RW DataWidth:0xc // Attention enable. Each PF attention vector is 12 bit. If the bit is set to 1, the corresponding bit in the attention vector is enabled. If the bit is set to 0, the corresponding bit in the attention vector is disabled.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
34861
#define IGU_REG_ATTENTION_ENABLE 0x18083cUL //Access:RW DataWidth:0xc Attention enable. Each PF attention vector is 12 bit. If the bit is set to 1, the corresponding bit in the attention vector is enabled. If the bit is set to 0, the corresponding bit in the attention vector is disabled. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
38078
#define IGU_REG_ATTENTION_ENABLE 0x18083cUL //Access:RW DataWidth:0xc // Attention enable. Each PF attention vector is 12 bit. If the bit is set to 1, the corresponding bit in the attention vector is enabled. If the bit is set to 0, the corresponding bit in the attention vector is disabled.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
38078
#define IGU_REG_ATTENTION_ENABLE 0x18083cUL //Access:RW DataWidth:0xc // Attention enable. Each PF attention vector is 12 bit. If the bit is set to 1, the corresponding bit in the attention vector is enabled. If the bit is set to 0, the corresponding bit in the attention vector is disabled.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
38078
#define IGU_REG_ATTENTION_ENABLE 0x18083cUL //Access:RW DataWidth:0xc // Attention enable. Each PF attention vector is 12 bit. If the bit is set to 1, the corresponding bit in the attention vector is enabled. If the bit is set to 0, the corresponding bit in the attention vector is disabled.