GRC_REG_TIMEOUT_ATTN_ACCESS_VALID
#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID 0x050054UL //Access:RW DataWidth:0x1 // When asserted, = 1, indicates that the timeout_attn_access_data_0 and timeout_attn_access_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID 0x050054UL //Access:RW DataWidth:0x1 When asserted, = 1, indicates that the timeout_attn_access_data_0 and timeout_attn_access_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW. Chips: BB_A0 BB_B0 K2
#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID 0x050054UL //Access:RW DataWidth:0x1 // When asserted, = 1, indicates that the timeout_attn_access_data_0 and timeout_attn_access_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID 0x050054UL //Access:RW DataWidth:0x1 // When asserted, = 1, indicates that the timeout_attn_access_data_0 and timeout_attn_access_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.
#define GRC_REG_TIMEOUT_ATTN_ACCESS_VALID 0x050054UL //Access:RW DataWidth:0x1 // When asserted, = 1, indicates that the timeout_attn_access_data_0 and timeout_attn_access_data_1 registers contain valid data. While asserted these registers will not latch new data in case the event happened again. Asserted by the hardware, de-asserted by the SW.