Symbol: GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
36466
#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 0x05004cUL //Access:R DataWidth:0x1c // Holds the data regarding the last access that caused timeout interrupt. Bits [22:0]: Address (4 bytes resolution). Bit [23]: Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 = dmae.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
33080
#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 0x05004cUL //Access:R DataWidth:0x1c Holds the data regarding the last access that caused timeout interrupt. Bits [22:0]: Address (4 bytes resolution). Bit [23]: Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 = dmae. Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
36410
#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 0x05004cUL //Access:R DataWidth:0x1c // Holds the data regarding the last access that caused timeout interrupt. Bits [22:0]: Address (4 bytes resolution). Bit [23]: Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 = dmae.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
36410
#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 0x05004cUL //Access:R DataWidth:0x1c // Holds the data regarding the last access that caused timeout interrupt. Bits [22:0]: Address (4 bytes resolution). Bit [23]: Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 = dmae.
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
36410
#define GRC_REG_TIMEOUT_ATTN_ACCESS_DATA_0 0x05004cUL //Access:R DataWidth:0x1c // Holds the data regarding the last access that caused timeout interrupt. Bits [22:0]: Address (4 bytes resolution). Bit [23]: Wr/rd. If = 1 it is write, if = 0 it is read. Bits [27:24]: Master. The decoding: 1 = pxp. 2 = mcp. 3 = msdm. 4 = psdm. 5 = ysdm. 6 = usdm. 7 = tsdm. 8 = xsdm. 9 = dbu. 10 = dmae.