Symbol: GRC_REG_DBG_FORCE_FRAME
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr.h
36492
#define GRC_REG_DBG_FORCE_FRAME 0x0500b4UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_ah_compile15.h
33106
#define GRC_REG_DBG_FORCE_FRAME 0x0500b4UL //Access:RW DataWidth:0x4 DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift). Chips: BB_A0 BB_B0 K2
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_bb.h
36436
#define GRC_REG_DBG_FORCE_FRAME 0x0500b4UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_e5.h
36436
#define GRC_REG_DBG_FORCE_FRAME 0x0500b4UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift).
usr/src/uts/common/io/qede/579xx/hsi/hw/reg_addr_k2.h
36436
#define GRC_REG_DBG_FORCE_FRAME 0x0500b4UL //Access:RW DataWidth:0x4 // DBMUX register. bit mask for forcing the frame signal per dword (128bit line) / qword (256bit line) (before shift).