src/add-ons/accelerants/s3/register_io.h

43

void WriteReg32(uint32 addr, uint32 value);

src/add-ons/accelerants/s3/savage_mode.cpp

106

WriteReg32(PRI_STREAM_STRIDE,

src/add-ons/accelerants/s3/savage_mode.cpp

115

WriteReg32(S3_GLOBAL_GBD_REG, bci_enable | S3_LITTLE_ENDIAN | S3_BD64);

src/add-ons/accelerants/s3/savage_mode.cpp

122

WriteReg32(ADVANCED_FUNC_CTRL, ulTmp);

src/add-ons/accelerants/s3/savage_mode.cpp

156

WriteReg32(PRI_STREAM_FBUF_ADDR0, si.frameBufferOffset & 0x7fffff);

src/add-ons/accelerants/s3/savage_mode.cpp

157

WriteReg32(PRI_STREAM_FBUF_ADDR1, si.frameBufferOffset & 0x7fffff);

src/add-ons/accelerants/s3/savage_mode.cpp

158

WriteReg32(PRI_STREAM2_FBUF_ADDR0, si.frameBufferOffset & 0x7fffff);

src/add-ons/accelerants/s3/savage_mode.cpp

159

WriteReg32(PRI_STREAM2_FBUF_ADDR1, si.frameBufferOffset & 0x7fffff);

src/add-ons/accelerants/s3/savage_mode.cpp

170

WriteReg32(PRI_STREAM_STRIDE,

src/add-ons/accelerants/s3/savage_mode.cpp

173

WriteReg32(PRI_STREAM2_STRIDE,

src/add-ons/accelerants/s3/savage_mode.cpp

177

WriteReg32(S3_GLOBAL_GBD_REG, bci_enable | S3_LITTLE_ENDIAN | S3_BD64);

src/add-ons/accelerants/s3/savage_mode.cpp

221

WriteReg32(PRI_STREAM_STRIDE,

src/add-ons/accelerants/s3/savage_mode.cpp

224

WriteReg32(PRI_STREAM2_STRIDE,

src/add-ons/accelerants/s3/savage_mode.cpp

229

WriteReg32(PRI_STREAM_FBUF_ADDR0, si.frameBufferOffset);

src/add-ons/accelerants/s3/savage_mode.cpp

230

WriteReg32(PRI_STREAM_FBUF_ADDR1, 0x80000000);

src/add-ons/accelerants/s3/savage_mode.cpp

231

WriteReg32(PRI_STREAM2_FBUF_ADDR0, (si.frameBufferOffset & 0xfffffffc) | 0x80000000);

src/add-ons/accelerants/s3/savage_mode.cpp

232

WriteReg32(PRI_STREAM2_FBUF_ADDR1, si.frameBufferOffset & 0xfffffffc);

src/add-ons/accelerants/s3/savage_mode.cpp

235

WriteReg32(S3_GLOBAL_GBD_REG, bci_enable | S3_BD64 | 0x10000000);

src/add-ons/accelerants/s3/savage_mode.cpp

246

WriteReg32(PRI_STREAM_FBUF_ADDR0, si.frameBufferOffset);

src/add-ons/accelerants/s3/savage_mode.cpp

247

WriteReg32(PRI_STREAM2_FBUF_ADDR0, si.frameBufferOffset);

src/add-ons/accelerants/s3/savage_mode.cpp

258

WriteReg32(PRI_STREAM_STRIDE, ((mode.bytesPerRow << 4) & 0x7ff0));

src/add-ons/accelerants/s3/savage_mode.cpp

259

WriteReg32(PRI_STREAM2_STRIDE, ((mode.bytesPerRow << 4) & 0x7ff0));

src/add-ons/accelerants/s3/savage_mode.cpp

270

WriteReg32(S3_GLOBAL_GBD_REG, bci_enable | S3_BD64 | 0x10000000);

src/add-ons/accelerants/s3/savage_mode.cpp

331

WriteReg32(0x8128, ~0); // enable all write planes

src/add-ons/accelerants/s3/savage_mode.cpp

332

WriteReg32(0x812C, ~0); // enable all read planes

src/add-ons/accelerants/s3/savage_mode.cpp

340

WriteReg32(0x48C18, ReadReg32(0x48C18) & 0x3FF0); // Disable BCI

src/add-ons/accelerants/s3/savage_mode.cpp

346

WriteReg32(0x48C14, (si.cobOffset >> 11) | (si.cobSizeIndex << 29));

src/add-ons/accelerants/s3/savage_mode.cpp

349

WriteReg32(0x48C10, 0x78207220);

src/add-ons/accelerants/s3/savage_mode.cpp

351

WriteReg32(0x48C0C, 0);

src/add-ons/accelerants/s3/savage_mode.cpp

353

WriteReg32(0x48C18, ReadReg32(0x48C18) | 0x0C);

src/add-ons/accelerants/s3/savage_mode.cpp

366

WriteReg32(0x48C18, ReadReg32(0x48C18) & 0x3FF0); // Disable BCI

src/add-ons/accelerants/s3/savage_mode.cpp

367

WriteReg32(0x48C10, 0x00700040);

src/add-ons/accelerants/s3/savage_mode.cpp

368

WriteReg32(0x48C0C, 0);

src/add-ons/accelerants/s3/savage_mode.cpp

369

WriteReg32(0x48C18, ReadReg32(0x48C18) | 0x08); // enable BCI without COB

src/add-ons/accelerants/s3/savage_mode.cpp

376

WriteReg32(0x48C18, 0);

src/add-ons/accelerants/s3/savage_mode.cpp

378

WriteReg32(0x48C18, (si.cobOffset >> 7) | (si.cobSizeIndex));

src/add-ons/accelerants/s3/savage_mode.cpp

380

WriteReg32(0x48A30, 0);

src/add-ons/accelerants/s3/savage_mode.cpp

382

WriteReg32(0x48C18, ReadReg32(0x48C18) | 0x00280000);

src/add-ons/accelerants/s3/savage_mode.cpp

409

WriteReg32(DEST_SRC_STR, mode.bytesPerRow << 16 | mode.bytesPerRow);

src/add-ons/accelerants/s3/savage_mode.cpp

440

WriteReg32(SRC_BASE, 0);

src/add-ons/accelerants/s3/savage_mode.cpp

441

WriteReg32(DEST_BASE, 0);

src/add-ons/accelerants/s3/savage_mode.cpp

442

WriteReg32(CLIP_L_R, ((0) << 16) | mode.timing.h_display);

src/add-ons/accelerants/s3/savage_mode.cpp

443

WriteReg32(CLIP_T_B, ((0) << 16) | mode.timing.v_display);

src/add-ons/accelerants/s3/savage_mode.cpp

444

WriteReg32(MONO_PAT_0, ~0);

src/add-ons/accelerants/s3/savage_mode.cpp

445

WriteReg32(MONO_PAT_1, ~0);

src/add-ons/accelerants/s3/savage_mode.cpp

48

WriteReg32(PRI_STREAM_FBUF_ADDR0, 0);

src/add-ons/accelerants/s3/savage_mode.cpp

49

WriteReg32(PRI_STREAM_FBUF_ADDR1, 0);

src/add-ons/accelerants/s3/savage_mode.cpp

60

WriteReg32(PRI_STREAM_STRIDE,

src/add-ons/accelerants/s3/savage_mode.cpp

69

WriteReg32(S3_GLOBAL_GBD_REG, bci_enable | S3_LITTLE_ENDIAN | S3_BD64);

src/add-ons/accelerants/s3/savage_mode.cpp

76

WriteReg32(ADVANCED_FUNC_CTRL, ulTmp);

src/add-ons/accelerants/s3/savage_mode.cpp

811

WriteReg32(PRI_STREAM_FBUF_ADDR0, address & 0xFFFFFFFC);

src/add-ons/accelerants/s3/savage_mode.cpp

812

WriteReg32(PRI_STREAM_FBUF_ADDR1, address & 0xFFFFFFFC);

src/add-ons/accelerants/s3/savage_mode.cpp

815

WriteReg32(PRI_STREAM_FBUF_ADDR0, 0x80000000);

src/add-ons/accelerants/s3/savage_mode.cpp

816

WriteReg32(PRI_STREAM_FBUF_ADDR1, address & 0xFFFFFFF8);

src/add-ons/accelerants/s3/savage_mode.cpp

820

WriteReg32(PRI_STREAM_FBUF_ADDR0, (address & 0xFFFFFFF8));

src/add-ons/accelerants/s3/savage_mode.cpp

821

WriteReg32(PRI_STREAM2_FBUF_ADDR0, (address & 0xFFFFFFF8));

src/add-ons/accelerants/s3/savage_mode.cpp

824

WriteReg32(PRI_STREAM_FBUF_ADDR0, address | 0xFFFFFFFC);

src/add-ons/accelerants/s3/savage_mode.cpp

825

WriteReg32(PRI_STREAM_FBUF_ADDR1, address | 0x80000000);

src/add-ons/accelerants/s3/savage_mode.cpp

94

WriteReg32(PRI_STREAM_FBUF_ADDR0, 0);

src/add-ons/accelerants/s3/savage_mode.cpp

95

WriteReg32(PRI_STREAM_FBUF_ADDR1, 0);

src/add-ons/accelerants/s3/trio64_draw.cpp

27

WriteReg32(FRGD_COLOR, color);

src/add-ons/accelerants/s3/trio64_draw.cpp

55

WriteReg32(FRGD_COLOR, color);

src/add-ons/accelerants/s3/trio64_mode.cpp

257

WriteReg32(WRT_MASK, ~0); // enable all planes

src/add-ons/accelerants/s3/virge_draw.cpp

107

WriteReg32(RWIDTH_HEIGHT, ((w - 1) << 16) + h);

src/add-ons/accelerants/s3/virge_draw.cpp

108

WriteReg32(RDEST_XY, (x << 16) | y);

src/add-ons/accelerants/s3/virge_draw.cpp

109

WriteReg32(CMD_SET, cmd);

src/add-ons/accelerants/s3/virge_draw.cpp

153

WriteReg32(RWIDTH_HEIGHT, ((width) << 16) | (height + 1));

src/add-ons/accelerants/s3/virge_draw.cpp

154

WriteReg32(RSRC_XY, (src_x << 16) | src_y);

src/add-ons/accelerants/s3/virge_draw.cpp

155

WriteReg32(RDEST_XY, (dest_x << 16) | dest_y);

src/add-ons/accelerants/s3/virge_draw.cpp

156

WriteReg32(CMD_SET, cmd);

src/add-ons/accelerants/s3/virge_draw.cpp

43

WriteReg32(PAT_FG_CLR, color);

src/add-ons/accelerants/s3/virge_draw.cpp

44

WriteReg32(RWIDTH_HEIGHT, ((w - 1) << 16) | h);

src/add-ons/accelerants/s3/virge_draw.cpp

45

WriteReg32(RDEST_XY, (x << 16) | y);

src/add-ons/accelerants/s3/virge_draw.cpp

46

WriteReg32(CMD_SET, cmd);

src/add-ons/accelerants/s3/virge_draw.cpp

81

WriteReg32(PAT_FG_CLR, color);

src/add-ons/accelerants/s3/virge_draw.cpp

82

WriteReg32(RWIDTH_HEIGHT, ((w - 1) << 16) | 1);

src/add-ons/accelerants/s3/virge_draw.cpp

83

WriteReg32(RDEST_XY, (x << 16) | y);

src/add-ons/accelerants/s3/virge_draw.cpp

84

WriteReg32(CMD_SET, cmd);

src/add-ons/accelerants/s3/virge_mode.cpp

137

WriteReg32(DEST_SRC_STR, mode.bytesPerRow << 16 | mode.bytesPerRow);

src/add-ons/accelerants/s3/virge_mode.cpp

160

WriteReg32(DEST_SRC_STR, mode.bytesPerRow << 16 | mode.bytesPerRow);

src/add-ons/accelerants/s3/virge_mode.cpp

171

WriteReg32(SRC_BASE, 0);

src/add-ons/accelerants/s3/virge_mode.cpp

172

WriteReg32(DEST_BASE, 0);

src/add-ons/accelerants/s3/virge_mode.cpp

175

WriteReg32(CLIP_L_R, ((0) << 16) | mode.timing.h_display);

src/add-ons/accelerants/s3/virge_mode.cpp

176

WriteReg32(CLIP_T_B, ((0) << 16) | mode.timing.v_display);

src/add-ons/accelerants/s3/virge_mode.cpp

177

WriteReg32(MONO_PAT_0, ~0);

src/add-ons/accelerants/s3/virge_mode.cpp

178

WriteReg32(MONO_PAT_1, ~0);

src/add-ons/accelerants/s3/virge_mode.cpp

264

WriteReg32(FIFO_CONTROL_REG, 0xC000);

src/add-ons/accelerants/s3/virge_mode.cpp

59

WriteReg32(CMD_SET, CMD_NOP); // turn off auto-execute

src/add-ons/accelerants/s3/virge_mode.cpp

60

WriteReg32(SRC_BASE, 0);

src/add-ons/accelerants/s3/virge_mode.cpp

61

WriteReg32(DEST_BASE, 0);

src/add-ons/accelerants/s3/virge_mode.cpp

62

WriteReg32(DEST_SRC_STR, mode.bytesPerRow | (mode.bytesPerRow << 16));

src/add-ons/accelerants/s3/virge_mode.cpp

64

WriteReg32(CLIP_L_R, ((0) << 16) | mode.timing.h_display);

src/add-ons/accelerants/s3/virge_mode.cpp

65

WriteReg32(CLIP_T_B, ((0) << 16) | mode.timing.v_display);

src/add-ons/accelerants/s3/virge_mode.cpp

82

WriteReg32(CMD_SET, CMD_NOP);

src/add-ons/kernel/busses/usb/uhci.cpp

589

WriteReg32(UHCI_FRBASEADD, (uint32)physicalAddress);

src/add-ons/kernel/busses/usb/uhci.h

204

inline void WriteReg32(uint32 reg, uint32 value);