WriteOpReg
WriteOpReg(portRegister, portStatus | EHCI_PORTSC_PORTPOWER);
WriteOpReg(portRegister, portStatus & ~EHCI_PORTSC_ENABLE);
WriteOpReg(portRegister, portStatus & ~EHCI_PORTSC_PORTPOWER);
WriteOpReg(portRegister, portStatus | EHCI_PORTSC_CONNCHANGE);
WriteOpReg(portRegister, portStatus | EHCI_PORTSC_ENABLECHANGE);
WriteOpReg(portRegister, portStatus | EHCI_PORTSC_OCCHANGE);
WriteOpReg(portRegister, portStatus | EHCI_PORTSC_PORTOWNER);
WriteOpReg(portRegister, (portStatus & ~EHCI_PORTSC_ENABLE)
WriteOpReg(portRegister, portStatus & ~EHCI_PORTSC_PORTRESET);
WriteOpReg(portRegister, portStatus | EHCI_PORTSC_PORTOWNER);
WriteOpReg(portRegister, portStatus | EHCI_PORTSC_SUSPEND);
WriteOpReg(EHCI_USBCMD, 0);
WriteOpReg(EHCI_USBCMD, EHCI_USBCMD_HCRESET);
WriteOpReg(EHCI_USBSTS, status);
WriteOpReg(EHCI_USBSTS, status);
WriteOpReg(EHCI_USBCMD, ReadOpReg(EHCI_USBCMD) | EHCI_USBCMD_INTONAAD);
WriteOpReg(EHCI_USBINTR, 0);
WriteOpReg(EHCI_CTRDSSEGMENT, 0);
WriteOpReg(EHCI_USBINTR, fEnabledInterrupts);
WriteOpReg(EHCI_PERIODICLISTBASE, (uint32)physicalAddress);
WriteOpReg(EHCI_ASYNCLISTADDR, (uint32)fAsyncQueueHead->this_phy);
WriteOpReg(EHCI_USBCMD, 0);
WriteOpReg(EHCI_CONFIGFLAG, 0);
WriteOpReg(EHCI_USBCMD, config | EHCI_USBCMD_RUNSTOP
WriteOpReg(EHCI_CONFIGFLAG, EHCI_CONFIGFLAG_FLAG);
inline void WriteOpReg(uint32 reg, uint32 value);
WriteOpReg(portRegister, portStatus | PS_LWS | PS_XDEV_U3);
WriteOpReg(portRegister, portStatus | PS_PR);
WriteOpReg(portRegister, portStatus | PS_PP);
WriteOpReg(portRegister, portStatus | PS_XDEV_U0 | PS_LWS);
WriteOpReg(portRegister, portStatus | PS_PED);
WriteOpReg(portRegister, portStatus & ~PS_PP);
WriteOpReg(portRegister, portStatus | PS_CSC);
WriteOpReg(portRegister, portStatus | PS_PEC);
WriteOpReg(portRegister, portStatus | PS_OCC);
WriteOpReg(portRegister, portStatus | PS_PRC);
WriteOpReg(portRegister, portStatus | PS_WRC);
WriteOpReg(portRegister, portStatus | PS_PLC);
WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) & ~CMD_RUN);
WriteOpReg(XHCI_CMD, ReadOpReg(XHCI_CMD) | CMD_HCRST);
WriteOpReg(XHCI_STS, status);
WriteOpReg(XHCI_CMD, 0);
WriteOpReg(XHCI_CONFIG, fSlotCount);
WriteOpReg(XHCI_STS, ReadOpReg(XHCI_STS));
WriteOpReg(XHCI_DNCTRL, 0);
WriteOpReg(XHCI_DCBAAP_LO, (uint32)dmaAddress);
WriteOpReg(XHCI_DCBAAP_HI, (uint32)(dmaAddress >> 32));
WriteOpReg(XHCI_CRCR_LO, CRCR_CS);
WriteOpReg(XHCI_CRCR_HI, 0);
WriteOpReg(XHCI_CRCR_LO, CRCR_CA);
WriteOpReg(XHCI_CRCR_HI, 0);
WriteOpReg(XHCI_CRCR_LO, (uint32)dmaAddress | CRCR_RCS);
WriteOpReg(XHCI_CRCR_HI, (uint32)(dmaAddress >> 32));
WriteOpReg(XHCI_CMD, CMD_RUN | CMD_INTE | CMD_HSEE);
inline void WriteOpReg(uint32 reg, uint32 value);