src/add-ons/accelerants/3dfx/3dfx_mode.cpp

331

WriteCrtcReg(j, crtc[j]);

src/add-ons/accelerants/3dfx/3dfx_mode.cpp

333

WriteCrtcReg(0x1a, cr1a);

src/add-ons/accelerants/3dfx/3dfx_mode.cpp

334

WriteCrtcReg(0x1b, cr1b);

src/add-ons/accelerants/intel_810/i810_mode.cpp

148

WriteCrtcReg(0x11, crtc[0x11] & ~0x80);

src/add-ons/accelerants/intel_810/i810_mode.cpp

151

WriteCrtcReg(j, crtc[j]);

src/add-ons/accelerants/intel_810/i810_mode.cpp

155

WriteCrtcReg(EXT_VERT_TOTAL, vTotal >> 8);

src/add-ons/accelerants/intel_810/i810_mode.cpp

156

WriteCrtcReg(EXT_VERT_DISPLAY, vDisp_e >> 8);

src/add-ons/accelerants/intel_810/i810_mode.cpp

157

WriteCrtcReg(EXT_VERT_SYNC_START, vSync_s >> 8);

src/add-ons/accelerants/intel_810/i810_mode.cpp

158

WriteCrtcReg(EXT_VERT_BLANK_START, vBlank_s >> 8);

src/add-ons/accelerants/intel_810/i810_mode.cpp

159

WriteCrtcReg(EXT_HORIZ_TOTAL, hTotal >> 8);

src/add-ons/accelerants/intel_810/i810_mode.cpp

160

WriteCrtcReg(EXT_HORIZ_BLANK, (hBlank_e & 0x40) >> 6);

src/add-ons/accelerants/intel_810/i810_mode.cpp

161

WriteCrtcReg(EXT_OFFSET, offset >> 8);

src/add-ons/accelerants/intel_810/i810_mode.cpp

163

WriteCrtcReg(INTERLACE_CNTL, INTERLACE_DISABLE); // turn off interlace

src/add-ons/accelerants/intel_810/i810_mode.cpp

166

WriteCrtcReg(IO_CTNL, ReadCrtcReg(IO_CTNL) | EXTENDED_CRTC_CNTL);

src/add-ons/accelerants/intel_810/i810_mode.cpp

245

WriteCrtcReg(IO_CTNL, ReadCrtcReg(IO_CTNL) | EXTENDED_CRTC_CNTL);

src/add-ons/accelerants/intel_810/i810_mode.cpp

260

WriteCrtcReg(START_ADDR_LO, address & 0xff);

src/add-ons/accelerants/intel_810/i810_mode.cpp

261

WriteCrtcReg(START_ADDR_HI, (address >> 8) & 0xff);

src/add-ons/accelerants/intel_810/i810_mode.cpp

262

WriteCrtcReg(EXT_START_ADDR_HI, (address >> 22) & 0xff);

src/add-ons/accelerants/intel_810/i810_mode.cpp

263

WriteCrtcReg(EXT_START_ADDR,

src/add-ons/accelerants/s3/register_io.h

46

void WriteCrtcReg(uint8 index, uint8 value);

src/add-ons/accelerants/s3/register_io.h

47

void WriteCrtcReg(uint8 index, uint8 value, uint8 mask);

src/add-ons/accelerants/s3/savage_cursor.cpp

128

WriteCrtcReg(0x4d, (0xff & si.cursorOffset / 1024));

src/add-ons/accelerants/s3/savage_cursor.cpp

129

WriteCrtcReg(0x4c, (0xff00 & si.cursorOffset / 1024) >> 8);

src/add-ons/accelerants/s3/savage_cursor.cpp

134

WriteCrtcReg(0x4a, 0); // set foreground color stack low, mid, high bytes

src/add-ons/accelerants/s3/savage_cursor.cpp

135

WriteCrtcReg(0x4a, 0);

src/add-ons/accelerants/s3/savage_cursor.cpp

136

WriteCrtcReg(0x4a, 0);

src/add-ons/accelerants/s3/savage_cursor.cpp

139

WriteCrtcReg(0x4b, ~0); // set background color stack low, mid, high bytes

src/add-ons/accelerants/s3/savage_cursor.cpp

140

WriteCrtcReg(0x4b, ~0);

src/add-ons/accelerants/s3/savage_cursor.cpp

141

WriteCrtcReg(0x4b, ~0);

src/add-ons/accelerants/s3/savage_cursor.cpp

40

WriteCrtcReg(0x45, bShow ? 0x01 : 0x00, 0x01);

src/add-ons/accelerants/s3/savage_cursor.cpp

71

WriteCrtcReg( 0x4e, xOffset );

src/add-ons/accelerants/s3/savage_cursor.cpp

72

WriteCrtcReg( 0x4f, yOffset );

src/add-ons/accelerants/s3/savage_cursor.cpp

74

WriteCrtcReg( 0x47, (x & 0xff) );

src/add-ons/accelerants/s3/savage_cursor.cpp

75

WriteCrtcReg( 0x46, (x & 0x0700) >> 8 );

src/add-ons/accelerants/s3/savage_cursor.cpp

77

WriteCrtcReg( 0x49, (y & 0xff) );

src/add-ons/accelerants/s3/savage_cursor.cpp

78

WriteCrtcReg( 0x48, (y & 0x0700) >> 8 );

src/add-ons/accelerants/s3/savage_edid.cpp

46

WriteCrtcReg(index, value);

src/add-ons/accelerants/s3/savage_edid.cpp

84

WriteCrtcReg(DDCPort, tmp | 0x13);

src/add-ons/accelerants/s3/savage_edid.cpp

87

WriteCrtcReg(DDCPort, tmp);

src/add-ons/accelerants/s3/savage_init.cpp

161

WriteCrtcReg(0x40, 0x01, 0x01);

src/add-ons/accelerants/s3/savage_init.cpp

163

WriteCrtcReg(0x11, 0x00, 0x80); // unlock CRTC reg's 0-7 by clearing bit 7 of cr11

src/add-ons/accelerants/s3/savage_init.cpp

164

WriteCrtcReg(0x38, 0x48); // unlock sys regs CR20~CR3F

src/add-ons/accelerants/s3/savage_init.cpp

165

WriteCrtcReg(0x39, 0xa0); // unlock sys regs CR40~CRFF

src/add-ons/accelerants/s3/savage_init.cpp

168

WriteCrtcReg(0x40, 0x00, 0x01);

src/add-ons/accelerants/s3/savage_init.cpp

169

WriteCrtcReg(0x38, 0x48); // unlock sys regs CR20~CR3F

src/add-ons/accelerants/s3/savage_init.cpp

252

WriteCrtcReg(0x66, 0x02, 0x02); // set reset flag

src/add-ons/accelerants/s3/savage_init.cpp

254

WriteCrtcReg(0x66, 0x00, 0x02); // clear reset flag

src/add-ons/accelerants/s3/savage_mode.cpp

113

WriteCrtcReg(0x69, 0x80, 0x80);

src/add-ons/accelerants/s3/savage_mode.cpp

130

WriteCrtcReg(0x88, DISABLE_BLOCK_WRITE_2D, DISABLE_BLOCK_WRITE_2D);

src/add-ons/accelerants/s3/savage_mode.cpp

146

WriteCrtcReg(0x67, 0x08, 0x08);

src/add-ons/accelerants/s3/savage_mode.cpp

149

WriteCrtcReg(0x67, 0x08, 0x08);

src/add-ons/accelerants/s3/savage_mode.cpp

153

WriteCrtcReg(MEMORY_CTRL0_REG, 0x00, MEM_PS1 + MEM_PS2);

src/add-ons/accelerants/s3/savage_mode.cpp

185

WriteCrtcReg(0x78, 0xfb, 0xfb);

src/add-ons/accelerants/s3/savage_mode.cpp

201

WriteCrtcReg(0x67, 0x08, 0x08);

src/add-ons/accelerants/s3/savage_mode.cpp

204

WriteCrtcReg(0x67, 0x08, 0x08);

src/add-ons/accelerants/s3/savage_mode.cpp

210

WriteCrtcReg(0x65, 0x03, 0x03);

src/add-ons/accelerants/s3/savage_mode.cpp

267

WriteCrtcReg(0x67, 0x08, 0x08);

src/add-ons/accelerants/s3/savage_mode.cpp

272

WriteCrtcReg(0x73, 0x00, 0x20); // CR73 bit 5 = 0 block write disable

src/add-ons/accelerants/s3/savage_mode.cpp

309

WriteCrtcReg(0x50, 0xc1, 0xc1); // CR50, bit 7,6,0 = 111, Use GBD

src/add-ons/accelerants/s3/savage_mode.cpp

327

WriteCrtcReg(0x40, 0x01); // enable graphics engine

src/add-ons/accelerants/s3/savage_mode.cpp

328

WriteCrtcReg(0x31, 0x0c); // turn on 16-bit register access

src/add-ons/accelerants/s3/savage_mode.cpp

402

WriteCrtcReg(0x66, 0x02, 0x02);

src/add-ons/accelerants/s3/savage_mode.cpp

404

WriteCrtcReg(0x66, 0x00, 0x02);

src/add-ons/accelerants/s3/savage_mode.cpp

514

WriteCrtcReg(0x38, 0x48); // unlock sys regs CR20~CR3F

src/add-ons/accelerants/s3/savage_mode.cpp

515

WriteCrtcReg(0x39, 0xa0); // unlock sys regs CR40~CRFF

src/add-ons/accelerants/s3/savage_mode.cpp

525

WriteCrtcReg(0x67, regRec.CR67 & ~0x0e); // no STREAMS yet old and new

src/add-ons/accelerants/s3/savage_mode.cpp

534

WriteCrtcReg(0x5f, 0);

src/add-ons/accelerants/s3/savage_mode.cpp

547

WriteCrtcReg(0x66, regRec.CR66);

src/add-ons/accelerants/s3/savage_mode.cpp

548

WriteCrtcReg(0x3a, regRec.CR3A);

src/add-ons/accelerants/s3/savage_mode.cpp

549

WriteCrtcReg(0x58, regRec.CR58);

src/add-ons/accelerants/s3/savage_mode.cpp

550

WriteCrtcReg(0x53, regRec.CR53 & 0x7f);

src/add-ons/accelerants/s3/savage_mode.cpp

566

WriteCrtcReg(0x11, 0x00, 0x80); // unlock CRTC reg's 0-7 by clearing bit 7 of cr11

src/add-ons/accelerants/s3/savage_mode.cpp

569

WriteCrtcReg(j, regRec.CRTC[j]);

src/add-ons/accelerants/s3/savage_mode.cpp

583

WriteCrtcReg(0x53, regRec.CR53);

src/add-ons/accelerants/s3/savage_mode.cpp

584

WriteCrtcReg(0x5d, regRec.CR5D);

src/add-ons/accelerants/s3/savage_mode.cpp

585

WriteCrtcReg(0x5e, regRec.CR5E);

src/add-ons/accelerants/s3/savage_mode.cpp

586

WriteCrtcReg(0x3b, regRec.CR3B);

src/add-ons/accelerants/s3/savage_mode.cpp

587

WriteCrtcReg(0x3c, regRec.CR3C);

src/add-ons/accelerants/s3/savage_mode.cpp

588

WriteCrtcReg(0x43, regRec.CR43);

src/add-ons/accelerants/s3/savage_mode.cpp

589

WriteCrtcReg(0x65, regRec.CR65);

src/add-ons/accelerants/s3/savage_mode.cpp

592

WriteCrtcReg(0x67, regRec.CR67 & ~0x0e); // no streams for new and old streams engines

src/add-ons/accelerants/s3/savage_mode.cpp

595

WriteCrtcReg(0x34, regRec.CR34);

src/add-ons/accelerants/s3/savage_mode.cpp

596

WriteCrtcReg(0x42, regRec.CR42);

src/add-ons/accelerants/s3/savage_mode.cpp

597

WriteCrtcReg(0x45, regRec.CR45);

src/add-ons/accelerants/s3/savage_mode.cpp

598

WriteCrtcReg(0x50, regRec.CR50);

src/add-ons/accelerants/s3/savage_mode.cpp

599

WriteCrtcReg(0x51, regRec.CR51);

src/add-ons/accelerants/s3/savage_mode.cpp

603

WriteCrtcReg(0x69, regRec.CR69);

src/add-ons/accelerants/s3/savage_mode.cpp

605

WriteCrtcReg(0x33, regRec.CR33);

src/add-ons/accelerants/s3/savage_mode.cpp

606

WriteCrtcReg(0x86, regRec.CR86);

src/add-ons/accelerants/s3/savage_mode.cpp

607

WriteCrtcReg(0x88, regRec.CR88);

src/add-ons/accelerants/s3/savage_mode.cpp

608

WriteCrtcReg(0x90, regRec.CR90);

src/add-ons/accelerants/s3/savage_mode.cpp

609

WriteCrtcReg(0x91, regRec.CR91);

src/add-ons/accelerants/s3/savage_mode.cpp

612

WriteCrtcReg(0xb0, regRec.CRB0);

src/add-ons/accelerants/s3/savage_mode.cpp

632

WriteCrtcReg(0x67, regRec.CR67);

src/add-ons/accelerants/s3/savage_mode.cpp

635

WriteCrtcReg(0x66, cr66 | 0x80);

src/add-ons/accelerants/s3/savage_mode.cpp

637

WriteCrtcReg(0x3a, cr3a | 0x80);

src/add-ons/accelerants/s3/savage_mode.cpp

641

WriteCrtcReg(0x66, cr66);

src/add-ons/accelerants/s3/savage_mode.cpp

642

WriteCrtcReg(0x3a, cr3a);

src/add-ons/accelerants/s3/savage_mode.cpp

646

WriteCrtcReg(0x40, 0x01); // enable graphics engine

src/add-ons/accelerants/s3/savage_mode.cpp

67

WriteCrtcReg(0x69, 0x80, 0x80);

src/add-ons/accelerants/s3/savage_mode.cpp

84

WriteCrtcReg(0x88, DISABLE_BLOCK_WRITE_2D, DISABLE_BLOCK_WRITE_2D);

src/add-ons/accelerants/s3/trio64_cursor.cpp

102

WriteCrtcReg(0x4a, 0); // set foreground color stack low, mid, high bytes

src/add-ons/accelerants/s3/trio64_cursor.cpp

103

WriteCrtcReg(0x4a, 0);

src/add-ons/accelerants/s3/trio64_cursor.cpp

104

WriteCrtcReg(0x4a, 0);

src/add-ons/accelerants/s3/trio64_cursor.cpp

107

WriteCrtcReg(0x4b, ~0); // set background color stack low, mid, high bytes

src/add-ons/accelerants/s3/trio64_cursor.cpp

108

WriteCrtcReg(0x4b, ~0);

src/add-ons/accelerants/s3/trio64_cursor.cpp

109

WriteCrtcReg(0x4b, ~0);

src/add-ons/accelerants/s3/trio64_cursor.cpp

23

WriteCrtcReg(0x45, bShow ? 0x01 : 0x00, 0x01);

src/add-ons/accelerants/s3/trio64_cursor.cpp

48

WriteCrtcReg( 0x4e, xOffset );

src/add-ons/accelerants/s3/trio64_cursor.cpp

49

WriteCrtcReg( 0x4f, yOffset );

src/add-ons/accelerants/s3/trio64_cursor.cpp

51

WriteCrtcReg( 0x47, (x & 0xff) );

src/add-ons/accelerants/s3/trio64_cursor.cpp

52

WriteCrtcReg( 0x46, (x & 0x0700) >> 8 );

src/add-ons/accelerants/s3/trio64_cursor.cpp

54

WriteCrtcReg( 0x49, (y & 0xff) );

src/add-ons/accelerants/s3/trio64_cursor.cpp

55

WriteCrtcReg( 0x48, (y & 0x0700) >> 8 );

src/add-ons/accelerants/s3/trio64_cursor.cpp

96

WriteCrtcReg(0x4c, (0x0f00 & si.cursorOffset / 1024) >> 8);

src/add-ons/accelerants/s3/trio64_cursor.cpp

97

WriteCrtcReg(0x4d, (0xff & si.cursorOffset / 1024));

src/add-ons/accelerants/s3/trio64_init.cpp

102

WriteCrtcReg(0x86, 0x80);

src/add-ons/accelerants/s3/trio64_init.cpp

103

WriteCrtcReg(0x90, 0x00);

src/add-ons/accelerants/s3/trio64_init.cpp

94

WriteCrtcReg(0x38, 0x48); // unlock sys regs

src/add-ons/accelerants/s3/trio64_init.cpp

95

WriteCrtcReg(0x39, 0xa5); // unlock sys regs

src/add-ons/accelerants/s3/trio64_init.cpp

97

WriteCrtcReg(0x40, 0x01, 0x01);

src/add-ons/accelerants/s3/trio64_init.cpp

98

WriteCrtcReg(0x35, 0x00, 0x30);

src/add-ons/accelerants/s3/trio64_init.cpp

99

WriteCrtcReg(0x33, 0x20, 0x72);

src/add-ons/accelerants/s3/trio64_mode.cpp

159

WriteCrtcReg(0x33, cr33);

src/add-ons/accelerants/s3/trio64_mode.cpp

160

WriteCrtcReg(0x50, cr50); // set number of bits per pixel & display width

src/add-ons/accelerants/s3/trio64_mode.cpp

161

WriteCrtcReg(0x67, pixmux); // set pixel format

src/add-ons/accelerants/s3/trio64_mode.cpp

179

WriteCrtcReg(0x11, 0x00, 0x80); // unlock CRTC reg's 0-7 by clearing bit 7 of cr11

src/add-ons/accelerants/s3/trio64_mode.cpp

182

WriteCrtcReg(k, crtc[k]);

src/add-ons/accelerants/s3/trio64_mode.cpp

185

WriteCrtcReg(0x3b, cr3b);

src/add-ons/accelerants/s3/trio64_mode.cpp

186

WriteCrtcReg(0x3c, cr3c);

src/add-ons/accelerants/s3/trio64_mode.cpp

187

WriteCrtcReg(0x5d, cr5d);

src/add-ons/accelerants/s3/trio64_mode.cpp

188

WriteCrtcReg(0x5e, cr5e);

src/add-ons/accelerants/s3/trio64_mode.cpp

207

WriteCrtcReg(0x58, cr58 | 0x10, 0x13); // enable linear addressing & set memory size

src/add-ons/accelerants/s3/trio64_mode.cpp

209

WriteCrtcReg(0x31, 0x08);

src/add-ons/accelerants/s3/trio64_mode.cpp

210

WriteCrtcReg(0x32, 0x00);

src/add-ons/accelerants/s3/trio64_mode.cpp

211

WriteCrtcReg(0x34, 0x10);

src/add-ons/accelerants/s3/trio64_mode.cpp

212

WriteCrtcReg(0x3a, 0x15);

src/add-ons/accelerants/s3/trio64_mode.cpp

214

WriteCrtcReg(0x51, mode.bytesPerRow >> 7, 0x30);

src/add-ons/accelerants/s3/trio64_mode.cpp

215

WriteCrtcReg(0x53, 0x18, 0x18);

src/add-ons/accelerants/s3/trio64_mode.cpp

237

WriteCrtcReg(0x54, m << 3);

src/add-ons/accelerants/s3/trio64_mode.cpp

238

WriteCrtcReg(0x60, n);

src/add-ons/accelerants/s3/trio64_mode.cpp

240

WriteCrtcReg(0x42, 0x00, 0x20); // disable interlace mode

src/add-ons/accelerants/s3/trio64_mode.cpp

241

WriteCrtcReg(0x66, 0x89, 0x8f);

src/add-ons/accelerants/s3/trio64_mode.cpp

296

WriteCrtcReg(0x0c, (base >> 8) & 0xff);

src/add-ons/accelerants/s3/trio64_mode.cpp

297

WriteCrtcReg(0x0d, base & 0xff);

src/add-ons/accelerants/s3/trio64_mode.cpp

298

WriteCrtcReg(0x31, base >> 12, 0x30); // put bits 16-17 in bits 4-5 of CR31

src/add-ons/accelerants/s3/trio64_mode.cpp

299

WriteCrtcReg(0x51, base >> 18, 0x03); // put bits 18-19 in bits 0-1 of CR51

src/add-ons/accelerants/s3/trio64_mode.cpp

85

WriteCrtcReg(0x38, 0x48); // unlock sys regs

src/add-ons/accelerants/s3/trio64_mode.cpp

86

WriteCrtcReg(0x39, 0xa5); // unlock sys regs

src/add-ons/accelerants/s3/trio64_mode.cpp

89

WriteCrtcReg(0x45, 0x00, 0x01); // turn off hardware cursor

src/add-ons/accelerants/s3/virge_cursor.cpp

102

WriteCrtcReg(0x4a, 0); // set foreground color stack low, mid, high bytes

src/add-ons/accelerants/s3/virge_cursor.cpp

103

WriteCrtcReg(0x4a, 0);

src/add-ons/accelerants/s3/virge_cursor.cpp

104

WriteCrtcReg(0x4a, 0);

src/add-ons/accelerants/s3/virge_cursor.cpp

107

WriteCrtcReg(0x4b, ~0); // set background color stack low, mid, high bytes

src/add-ons/accelerants/s3/virge_cursor.cpp

108

WriteCrtcReg(0x4b, ~0);

src/add-ons/accelerants/s3/virge_cursor.cpp

109

WriteCrtcReg(0x4b, ~0);

src/add-ons/accelerants/s3/virge_cursor.cpp

23

WriteCrtcReg(0x45, bShow ? 0x01 : 0x00, 0x01);

src/add-ons/accelerants/s3/virge_cursor.cpp

48

WriteCrtcReg( 0x4e, xOffset );

src/add-ons/accelerants/s3/virge_cursor.cpp

49

WriteCrtcReg( 0x4f, yOffset );

src/add-ons/accelerants/s3/virge_cursor.cpp

51

WriteCrtcReg( 0x47, (x & 0xff) );

src/add-ons/accelerants/s3/virge_cursor.cpp

52

WriteCrtcReg( 0x46, (x & 0x0700) >> 8 );

src/add-ons/accelerants/s3/virge_cursor.cpp

54

WriteCrtcReg( 0x49, (y & 0xff) );

src/add-ons/accelerants/s3/virge_cursor.cpp

55

WriteCrtcReg( 0x48, (y & 0x0700) >> 8 );

src/add-ons/accelerants/s3/virge_cursor.cpp

96

WriteCrtcReg(0x4d, (0xff & si.cursorOffset / 1024));

src/add-ons/accelerants/s3/virge_cursor.cpp

97

WriteCrtcReg(0x4c, (0x0f00 & si.cursorOffset / 1024) >> 8);

src/add-ons/accelerants/s3/virge_edid.cpp

101

WriteCrtcReg(DDCPort, tmp | 0x13);

src/add-ons/accelerants/s3/virge_edid.cpp

105

WriteCrtcReg(DDCPort, tmp);

src/add-ons/accelerants/s3/virge_edid.cpp

45

WriteCrtcReg(index, value);

src/add-ons/accelerants/s3/virge_init.cpp

102

WriteCrtcReg(0x40, 0x01, 0x01);

src/add-ons/accelerants/s3/virge_mode.cpp

113

WriteCrtcReg(resetidx, tmp);

src/add-ons/accelerants/s3/virge_mode.cpp

119

WriteCrtcReg(resetidx, tmp | 0x02);

src/add-ons/accelerants/s3/virge_mode.cpp

123

WriteCrtcReg(resetidx, tmp & ~0x02);

src/add-ons/accelerants/s3/virge_mode.cpp

128

WriteCrtcReg(resetidx, tmp);

src/add-ons/accelerants/s3/virge_mode.cpp

154

WriteCrtcReg(regIndex, tmp | 0x02);

src/add-ons/accelerants/s3/virge_mode.cpp

156

WriteCrtcReg(regIndex, tmp & ~0x02);

src/add-ons/accelerants/s3/virge_mode.cpp

266

WriteCrtcReg(0x67, 0x00, 0x0c); // disable STREAMS processor

src/add-ons/accelerants/s3/virge_mode.cpp

270

WriteCrtcReg(0x63, regRec.CR63);

src/add-ons/accelerants/s3/virge_mode.cpp

271

WriteCrtcReg(0x66, regRec.CR66);

src/add-ons/accelerants/s3/virge_mode.cpp

272

WriteCrtcReg(0x3a, regRec.CR3A);

src/add-ons/accelerants/s3/virge_mode.cpp

273

WriteCrtcReg(0x31, regRec.CR31);

src/add-ons/accelerants/s3/virge_mode.cpp

274

WriteCrtcReg(0x58, regRec.CR58);

src/add-ons/accelerants/s3/virge_mode.cpp

277

WriteCrtcReg(0x53, regRec.CR53);

src/add-ons/accelerants/s3/virge_mode.cpp

278

WriteCrtcReg(0x5d, regRec.CR5D);

src/add-ons/accelerants/s3/virge_mode.cpp

279

WriteCrtcReg(0x5e, regRec.CR5E);

src/add-ons/accelerants/s3/virge_mode.cpp

280

WriteCrtcReg(0x3b, regRec.CR3B);

src/add-ons/accelerants/s3/virge_mode.cpp

281

WriteCrtcReg(0x3c, regRec.CR3C);

src/add-ons/accelerants/s3/virge_mode.cpp

282

WriteCrtcReg(0x43, regRec.CR43);

src/add-ons/accelerants/s3/virge_mode.cpp

283

WriteCrtcReg(0x65, regRec.CR65);

src/add-ons/accelerants/s3/virge_mode.cpp

284

WriteCrtcReg(0x6d, regRec.CR6D);

src/add-ons/accelerants/s3/virge_mode.cpp

288

WriteCrtcReg(0x67, 0x50, 0xf0); // possible hardware bug on VX?

src/add-ons/accelerants/s3/virge_mode.cpp

290

WriteCrtcReg(0x67, regRec.CR67 & ~0x0c); // Don't enable STREAMS

src/add-ons/accelerants/s3/virge_mode.cpp

294

WriteCrtcReg(0x34, regRec.CR34);

src/add-ons/accelerants/s3/virge_mode.cpp

296

WriteCrtcReg(0x40, regRec.CR40);

src/add-ons/accelerants/s3/virge_mode.cpp

300

WriteCrtcReg(0x41, regRec.CR41);

src/add-ons/accelerants/s3/virge_mode.cpp

303

WriteCrtcReg(0x42, regRec.CR42);

src/add-ons/accelerants/s3/virge_mode.cpp

304

WriteCrtcReg(0x45, regRec.CR45);

src/add-ons/accelerants/s3/virge_mode.cpp

305

WriteCrtcReg(0x51, regRec.CR51);

src/add-ons/accelerants/s3/virge_mode.cpp

306

WriteCrtcReg(0x54, regRec.CR54);

src/add-ons/accelerants/s3/virge_mode.cpp

309

WriteCrtcReg(0x68, regRec.CR68);

src/add-ons/accelerants/s3/virge_mode.cpp

310

WriteCrtcReg(0x69, regRec.CR69);

src/add-ons/accelerants/s3/virge_mode.cpp

312

WriteCrtcReg(0x33, regRec.CR33);

src/add-ons/accelerants/s3/virge_mode.cpp

315

WriteCrtcReg(0x85, regRec.CR85);

src/add-ons/accelerants/s3/virge_mode.cpp

319

WriteCrtcReg(0x86, regRec.CR86);

src/add-ons/accelerants/s3/virge_mode.cpp

323

WriteCrtcReg(0x7b, regRec.CR7B);

src/add-ons/accelerants/s3/virge_mode.cpp

324

WriteCrtcReg(0x7d, regRec.CR7D);

src/add-ons/accelerants/s3/virge_mode.cpp

325

WriteCrtcReg(0x87, regRec.CR87);

src/add-ons/accelerants/s3/virge_mode.cpp

326

WriteCrtcReg(0x92, regRec.CR92);

src/add-ons/accelerants/s3/virge_mode.cpp

327

WriteCrtcReg(0x93, regRec.CR93);

src/add-ons/accelerants/s3/virge_mode.cpp

332

WriteCrtcReg(0x90, regRec.CR90);

src/add-ons/accelerants/s3/virge_mode.cpp

333

WriteCrtcReg(0x91, regRec.CR91);

src/add-ons/accelerants/s3/virge_mode.cpp

370

WriteCrtcReg(0x67, 0x50); // For possible bug on VX?!

src/add-ons/accelerants/s3/virge_mode.cpp

372

WriteCrtcReg(0x67, regRec.CR67);

src/add-ons/accelerants/s3/virge_mode.cpp

375

WriteCrtcReg(0x66, cr66 | 0x80);

src/add-ons/accelerants/s3/virge_mode.cpp

377

WriteCrtcReg(0x3a, regRec.CR3A | 0x80);

src/add-ons/accelerants/s3/virge_mode.cpp

392

WriteCrtcReg(0x85, 0x1f); // primary stream threshold

src/add-ons/accelerants/s3/virge_mode.cpp

397

WriteCrtcReg(0x11, 0x00, 0x80); // unlock CRTC reg's 0-7 by clearing bit 7 of cr11

src/add-ons/accelerants/s3/virge_mode.cpp

400

WriteCrtcReg(j, regRec.CRTC[j]);

src/add-ons/accelerants/s3/virge_mode.cpp

415

WriteCrtcReg(0x66, cr66);

src/add-ons/accelerants/s3/virge_mode.cpp

416

WriteCrtcReg(0x3a, regRec.CR3A);

src/add-ons/accelerants/s3/virge_mode.cpp

751

WriteCrtcReg(0x0c, (base >> 8) & 0xff);

src/add-ons/accelerants/s3/virge_mode.cpp

752

WriteCrtcReg(0x0d, base & 0xff);

src/add-ons/accelerants/s3/virge_mode.cpp

753

WriteCrtcReg(0x69, (base & 0x0F0000) >> 16);