WriteConfig
WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function, offset, 4,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
WriteConfig(dev->domain, dev->bus, dev->device, dev->function,
return WriteConfig(device->domain, device->bus, device->device,
return WriteConfig(device, PCI_interrupt_line, 1, newInterruptLineValue);
WriteConfig(device, capabilityOffset + PCI_pm_status, 2,
WriteConfig(device, offset + PCI_msi_address, 4,
WriteConfig(device, offset + PCI_msi_address_high, 4,
WriteConfig(device, offset + PCI_msi_data_64bit, 2,
WriteConfig(device, offset + PCI_msi_data, 2, info->data_value);
WriteConfig(device, offset + PCI_msi_control, 2, info->control_value);
WriteConfig(device, info->capability_offset + PCI_msi_control, 2,
WriteConfig(device, PCI_command, 2,
WriteConfig(device, info->capability_offset + PCI_msi_control, 2,
WriteConfig(device, info->capability_offset + PCI_msi_control, 2,
WriteConfig(device, PCI_command, 2,
WriteConfig(device, PCI_command, 2,
WriteConfig(device, info->capability_offset + PCI_msix_control, 2,
WriteConfig(device, info->capability_offset + PCI_ht_command, 2,
WriteConfig(device, info->capability_offset + PCI_msix_control, 2,
gPCI->WriteConfig(device, info->capability_offset + PCI_msix_control, 2,
gPCI->WriteConfig(domain, bus, device, function, offset, size, value);
WriteConfig(domain, bus, dev, function, PCI_command, 2, pcicmd);
WriteConfig(domain, bus, dev, function, PCI_primary_bus, 1, 0);
WriteConfig(domain, bus, dev, function, PCI_secondary_bus, 1, 0);
WriteConfig(domain, bus, dev, function, PCI_subordinate_bus, 1, 0);
WriteConfig(domain, bus, dev, function, PCI_primary_bus, 1, bus);
WriteConfig(domain, bus, dev, function, PCI_secondary_bus, 1,
WriteConfig(domain, bus, dev, function, PCI_subordinate_bus, 1, 255);
WriteConfig(domain, bus, dev, function, PCI_command, 2, pcicmd);
WriteConfig(domain, bus, dev, function, PCI_subordinate_bus, 1, lastUsedBusNumber);
status_t WriteConfig(uint8 domain, uint8 bus, uint8 device,
status_t WriteConfig(PCIDev *device, uint16 offset,
gPCI->WriteConfig(device->device, offset, size, value);
pci->WriteConfig(domain, bus, device, function, PCI_command, 2,
pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0xffffffff);
pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0);
pci->WriteConfig(domain, bus, device, function, 0x90, 1, map);
pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0xffffffff);
pci->WriteConfig(domain, bus, device, function, 0x24, 4, 0);
pci->WriteConfig(domain, bus, device, function, 0x24, 4, bar5);
pci->WriteConfig(domain, bus, device, function, PCI_command, 2, pcicmd);
pci->WriteConfig(domain, bus, device, function, 0x40, 4, val);
pci->WriteConfig(domain, bus, device, 1, 0x3c, 1, irq);
status_t WriteConfig(
->WriteConfig(bus, device, function, offset, size, value);
status_t WriteConfig(
->WriteConfig(bus, device, function, offset, size, value);
return X86PCIControllerMeth1::WriteConfig(bus, device, function, offset,
return fECAMPCIController.WriteConfig(bus, device, function, offset, size, value);
status_t WriteConfig(
virtual status_t WriteConfig(
status_t WriteConfig(
status_t WriteConfig(
->WriteConfig(bus, device, function, offset, size, value);
return WriteConfig(SET_STATUS, &control, 2);
return WriteConfig(ENABLE_UART, &enableUart, 2);
status_t result = WriteConfig(SET_BAUDRATE_DIVIDER, ÷r, 2);
return WriteConfig(SET_LINE_FORMAT, &data, 2);
status_t WriteConfig(CP210XRequest request, uint16_t* data,
status_t status = WriteConfig(fDataRate, fStatusLCR, fStatusMCR);
status = WriteConfig(fDataRate, fStatusLCR, fStatusMCR);
status_t WriteConfig(uint16 dataRate, uint8 lcr, uint8 mcr);