src/add-ons/accelerants/radeon_hd/bios.cpp

53

Write32(OUT, R600_SCRATCH_REG2, biosScratch2);

src/add-ons/accelerants/radeon_hd/bios.cpp

54

Write32(OUT, R600_SCRATCH_REG6, biosScratch6);

src/add-ons/accelerants/radeon_hd/bios.cpp

56

Write32(OUT, RADEON_BIOS_2_SCRATCH, biosScratch2);

src/add-ons/accelerants/radeon_hd/bios.cpp

57

Write32(OUT, RADEON_BIOS_6_SCRATCH, biosScratch6);

src/add-ons/accelerants/radeon_hd/connector.cpp

108

Write32(OUT, info->i2c.sclEnReg, scl);

src/add-ons/accelerants/radeon_hd/connector.cpp

113

Write32(OUT, info->i2c.sdaEnReg, sda);

src/add-ons/accelerants/radeon_hd/connector.cpp

48

Write32(OUT, info->i2c.sclMaskReg, buffer);

src/add-ons/accelerants/radeon_hd/connector.cpp

53

Write32(OUT, info->i2c.sclAReg, buffer);

src/add-ons/accelerants/radeon_hd/connector.cpp

55

Write32(OUT, info->i2c.sdaAReg, buffer);

src/add-ons/accelerants/radeon_hd/connector.cpp

60

Write32(OUT, info->i2c.sclEnReg, buffer);

src/add-ons/accelerants/radeon_hd/connector.cpp

62

Write32(OUT, info->i2c.sdaEnReg, buffer);

src/add-ons/accelerants/radeon_hd/connector.cpp

71

Write32(OUT, info->i2c.sclMaskReg, buffer);

src/add-ons/accelerants/radeon_hd/connector.cpp

81

Write32(OUT, info->i2c.sdaMaskReg, buffer);

src/add-ons/accelerants/radeon_hd/display.cpp

606

Write32(OUT, NI_INPUT_CSC_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

609

Write32(OUT, NI_PRESCALE_GRPH_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

611

Write32(OUT, NI_PRESCALE_OVL_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

613

Write32(OUT, NI_INPUT_GAMMA_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

618

Write32(OUT, EVERGREEN_DC_LUT_CONTROL + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

620

Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

621

Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

622

Write32(OUT, EVERGREEN_DC_LUT_BLACK_OFFSET_RED + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

624

Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + regs->crtcOffset, 0xffff);

src/add-ons/accelerants/radeon_hd/display.cpp

625

Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + regs->crtcOffset, 0xffff);

src/add-ons/accelerants/radeon_hd/display.cpp

626

Write32(OUT, EVERGREEN_DC_LUT_WHITE_OFFSET_RED + regs->crtcOffset, 0xffff);

src/add-ons/accelerants/radeon_hd/display.cpp

628

Write32(OUT, EVERGREEN_DC_LUT_RW_MODE, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

629

Write32(OUT, EVERGREEN_DC_LUT_WRITE_EN_MASK, 0x00000007);

src/add-ons/accelerants/radeon_hd/display.cpp

631

Write32(OUT, EVERGREEN_DC_LUT_RW_INDEX, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

633

Write32(OUT, EVERGREEN_DC_LUT_30_COLOR + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

638

Write32(OUT, NI_DEGAMMA_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

643

Write32(OUT, NI_GAMUT_REMAP_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

646

Write32(OUT, NI_REGAMMA_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

649

Write32(OUT, NI_OUTPUT_CSC_CONTROL + regs->crtcOffset,

src/add-ons/accelerants/radeon_hd/display.cpp

653

Write32(OUT, 0x6940 + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

670

Write32(OUT, AVIVO_DC_LUTA_CONTROL + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

672

Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

673

Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

674

Write32(OUT, AVIVO_DC_LUTA_BLACK_OFFSET_RED + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

676

Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + regs->crtcOffset, 0xffff);

src/add-ons/accelerants/radeon_hd/display.cpp

677

Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + regs->crtcOffset, 0xffff);

src/add-ons/accelerants/radeon_hd/display.cpp

678

Write32(OUT, AVIVO_DC_LUTA_WHITE_OFFSET_RED + regs->crtcOffset, 0xffff);

src/add-ons/accelerants/radeon_hd/display.cpp

680

Write32(OUT, AVIVO_DC_LUT_RW_SELECT, crtcID);

src/add-ons/accelerants/radeon_hd/display.cpp

681

Write32(OUT, AVIVO_DC_LUT_RW_MODE, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

682

Write32(OUT, AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);

src/add-ons/accelerants/radeon_hd/display.cpp

684

Write32(OUT, AVIVO_DC_LUT_RW_INDEX, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

686

Write32(OUT, AVIVO_DC_LUT_30_COLOR,

src/add-ons/accelerants/radeon_hd/display.cpp

690

Write32(OUT, AVIVO_D1GRPH_LUT_SEL + regs->crtcOffset, crtcID);

src/add-ons/accelerants/radeon_hd/display.cpp

802

Write32(OUT, regs->vgaControl, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

812

Write32(OUT, regs->grphPrimarySurfaceAddrHigh,

src/add-ons/accelerants/radeon_hd/display.cpp

814

Write32(OUT, regs->grphSecondarySurfaceAddrHigh,

src/add-ons/accelerants/radeon_hd/display.cpp

821

Write32(OUT, regs->grphPrimarySurfaceAddr, (fbAddress & 0xFFFFFFFF));

src/add-ons/accelerants/radeon_hd/display.cpp

822

Write32(OUT, regs->grphSecondarySurfaceAddr, (fbAddress & 0xFFFFFFFF));

src/add-ons/accelerants/radeon_hd/display.cpp

825

Write32(CRT, regs->grphControl, fbFormat);

src/add-ons/accelerants/radeon_hd/display.cpp

826

Write32(CRT, regs->grphSwapControl, fbSwap);

src/add-ons/accelerants/radeon_hd/display.cpp

855

Write32(CRT, regs->grphSurfaceOffsetX, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

856

Write32(CRT, regs->grphSurfaceOffsetY, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

857

Write32(CRT, regs->grphXStart, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

858

Write32(CRT, regs->grphYStart, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

859

Write32(CRT, regs->grphXEnd, mode->virtual_width);

src/add-ons/accelerants/radeon_hd/display.cpp

860

Write32(CRT, regs->grphYEnd, mode->virtual_height);

src/add-ons/accelerants/radeon_hd/display.cpp

861

Write32(CRT, regs->grphPitch, widthAligned);

src/add-ons/accelerants/radeon_hd/display.cpp

863

Write32(CRT, regs->grphEnable, 1);

src/add-ons/accelerants/radeon_hd/display.cpp

866

Write32(CRT, regs->modeDesktopHeight, mode->virtual_height);

src/add-ons/accelerants/radeon_hd/display.cpp

871

Write32(CRT, regs->viewportStart, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

872

Write32(CRT, regs->viewportSize,

src/add-ons/accelerants/radeon_hd/display.cpp

880

Write32(OUT, EVERGREEN_GRPH_FLIP_CONTROL + regs->crtcOffset, tmp);

src/add-ons/accelerants/radeon_hd/display.cpp

882

Write32(OUT, EVERGREEN_MASTER_UPDATE_MODE + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/display.cpp

888

Write32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset, tmp);

src/add-ons/accelerants/radeon_hd/display.cpp

890

Write32(OUT, AVIVO_D1MODE_MASTER_UPDATE_MODE + regs->crtcOffset, 0);

src/add-ons/accelerants/radeon_hd/encoder.cpp

1812

Write32(OUT, R600_SCRATCH_REG3, biosScratch3);

src/add-ons/accelerants/radeon_hd/encoder.cpp

1887

Write32(OUT, R600_SCRATCH_REG2, biosScratch2);

src/add-ons/accelerants/radeon_hd/encoder.cpp

2046

Write32(OUT, AVIVO_DP_VID_STREAM_CNTL, 0x201);

src/add-ons/accelerants/radeon_hd/encoder.cpp

2121

Write32(OUT, R600_SCRATCH_REG6, biosScratch6);

src/add-ons/accelerants/radeon_hd/encoder.cpp

382

Write32(OUT, regs->modeDataFormat, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

113

Write32(OUT, CP_ME_CNTL, CP_ME_HALT);

src/add-ons/accelerants/radeon_hd/gpu.cpp

175

Write32(OUT, GRBM_SOFT_RESET, tmp);

src/add-ons/accelerants/radeon_hd/gpu.cpp

178

Write32(OUT, GRBM_SOFT_RESET, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

183

Write32(OUT, GRBM_SOFT_RESET, tmp);

src/add-ons/accelerants/radeon_hd/gpu.cpp

186

Write32(OUT, GRBM_SOFT_RESET, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

193

Write32(OUT, CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);

src/add-ons/accelerants/radeon_hd/gpu.cpp

211

Write32(OUT, GRBM_SOFT_RESET, grbmReset);

src/add-ons/accelerants/radeon_hd/gpu.cpp

215

Write32(OUT, GRBM_SOFT_RESET, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

281

Write32(OUT, AVIVO_VGA_RENDER_CONTROL, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

282

Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 1);

src/add-ons/accelerants/radeon_hd/gpu.cpp

283

Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 1);

src/add-ons/accelerants/radeon_hd/gpu.cpp

284

Write32(OUT, AVIVO_D1CRTC_CONTROL, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

285

Write32(OUT, AVIVO_D2CRTC_CONTROL, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

286

Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

287

Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

288

Write32(OUT, AVIVO_D1VGA_CONTROL, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

289

Write32(OUT, AVIVO_D2VGA_CONTROL, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

296

Write32(OUT, AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->fb.vramStart);

src/add-ons/accelerants/radeon_hd/gpu.cpp

297

Write32(OUT, AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS, gInfo->fb.vramStart);

src/add-ons/accelerants/radeon_hd/gpu.cpp

298

Write32(OUT, AVIVO_D2GRPH_PRIMARY_SURFACE_ADDRESS, gInfo->fb.vramStart);

src/add-ons/accelerants/radeon_hd/gpu.cpp

299

Write32(OUT, AVIVO_D2GRPH_SECONDARY_SURFACE_ADDRESS, gInfo->fb.vramStart);

src/add-ons/accelerants/radeon_hd/gpu.cpp

301

Write32(OUT, AVIVO_VGA_MEMORY_BASE_ADDRESS, gInfo->fb.vramStart);

src/add-ons/accelerants/radeon_hd/gpu.cpp

304

Write32(OUT, AVIVO_VGA_HDP_CONTROL, gpuState->vgaHdpControl);

src/add-ons/accelerants/radeon_hd/gpu.cpp

308

Write32(OUT, AVIVO_D1VGA_CONTROL, gpuState->d1vgaControl);

src/add-ons/accelerants/radeon_hd/gpu.cpp

309

Write32(OUT, AVIVO_D2VGA_CONTROL, gpuState->d2vgaControl);

src/add-ons/accelerants/radeon_hd/gpu.cpp

310

Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 1);

src/add-ons/accelerants/radeon_hd/gpu.cpp

311

Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 1);

src/add-ons/accelerants/radeon_hd/gpu.cpp

312

Write32(OUT, AVIVO_D1CRTC_CONTROL, gpuState->d1crtcControl);

src/add-ons/accelerants/radeon_hd/gpu.cpp

313

Write32(OUT, AVIVO_D2CRTC_CONTROL, gpuState->d2crtcControl);

src/add-ons/accelerants/radeon_hd/gpu.cpp

314

Write32(OUT, AVIVO_D1CRTC_UPDATE_LOCK, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

315

Write32(OUT, AVIVO_D2CRTC_UPDATE_LOCK, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

316

Write32(OUT, AVIVO_VGA_RENDER_CONTROL, gpuState->vgaRenderControl);

src/add-ons/accelerants/radeon_hd/gpu.cpp

363

Write32(OUT, (0x2c14 + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

364

Write32(OUT, (0x2c18 + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

365

Write32(OUT, (0x2c1c + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

366

Write32(OUT, (0x2c20 + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

367

Write32(OUT, (0x2c24 + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

369

Write32(OUT, R600_HDP_REG_COHERENCY_FLUSH_CNTL, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

379

Write32(OUT, R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR,

src/add-ons/accelerants/radeon_hd/gpu.cpp

381

Write32(OUT, R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

src/add-ons/accelerants/radeon_hd/gpu.cpp

384

Write32(OUT, R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

388

Write32(OUT, R600_MC_VM_FB_LOCATION, tmp);

src/add-ons/accelerants/radeon_hd/gpu.cpp

389

Write32(OUT, R600_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));

src/add-ons/accelerants/radeon_hd/gpu.cpp

390

Write32(OUT, R600_HDP_NONSURFACE_INFO, (2 << 7));

src/add-ons/accelerants/radeon_hd/gpu.cpp

391

Write32(OUT, R600_HDP_NONSURFACE_SIZE, 0x3FFFFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

398

Write32(OUT, R600_MC_VM_AGP_BASE, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

399

Write32(OUT, R600_MC_VM_AGP_TOP, 0x0FFFFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

400

Write32(OUT, R600_MC_VM_AGP_BOT, 0x0FFFFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

408

Write32(OUT, 0x000300, Read32(OUT, 0x000300) & 0xFFFCFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

421

Write32(OUT, (0x2c14 + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

422

Write32(OUT, (0x2c18 + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

423

Write32(OUT, (0x2c1c + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

424

Write32(OUT, (0x2c20 + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

425

Write32(OUT, (0x2c24 + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

438

Write32(OUT, AVIVO_VGA_HDP_CONTROL, AVIVO_VGA_MEMORY_DISABLE);

src/add-ons/accelerants/radeon_hd/gpu.cpp

441

Write32(OUT, R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR,

src/add-ons/accelerants/radeon_hd/gpu.cpp

443

Write32(OUT, R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

src/add-ons/accelerants/radeon_hd/gpu.cpp

446

Write32(OUT, R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

450

Write32(OUT, R700_MC_VM_FB_LOCATION, tmp);

src/add-ons/accelerants/radeon_hd/gpu.cpp

451

Write32(OUT, R700_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));

src/add-ons/accelerants/radeon_hd/gpu.cpp

452

Write32(OUT, R700_HDP_NONSURFACE_INFO, (2 << 7));

src/add-ons/accelerants/radeon_hd/gpu.cpp

453

Write32(OUT, R700_HDP_NONSURFACE_SIZE, 0x3FFFFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

460

Write32(OUT, R700_MC_VM_AGP_BASE, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

461

Write32(OUT, R700_MC_VM_AGP_TOP, 0x0FFFFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

462

Write32(OUT, R700_MC_VM_AGP_BOT, 0x0FFFFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

470

Write32(OUT, 0x000300, Read32(OUT, 0x000300) & 0xFFFCFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

483

Write32(OUT, (0x2c14 + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

484

Write32(OUT, (0x2c18 + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

485

Write32(OUT, (0x2c1c + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

486

Write32(OUT, (0x2c20 + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

487

Write32(OUT, (0x2c24 + j), 0x00000000);

src/add-ons/accelerants/radeon_hd/gpu.cpp

489

Write32(OUT, EVERGREEN_HDP_REG_COHERENCY_FLUSH_CNTL, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

498

Write32(OUT, AVIVO_VGA_HDP_CONTROL, AVIVO_VGA_MEMORY_DISABLE);

src/add-ons/accelerants/radeon_hd/gpu.cpp

501

Write32(OUT, EVERGREEN_MC_VM_SYSTEM_APERTURE_LOW_ADDR,

src/add-ons/accelerants/radeon_hd/gpu.cpp

503

Write32(OUT, EVERGREEN_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,

src/add-ons/accelerants/radeon_hd/gpu.cpp

506

Write32(OUT, EVERGREEN_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

515

Write32(OUT, EVERGREEN_MC_FUS_VM_FB_OFFSET, tmp);

src/add-ons/accelerants/radeon_hd/gpu.cpp

521

Write32(OUT, EVERGREEN_MC_VM_FB_LOCATION, tmp);

src/add-ons/accelerants/radeon_hd/gpu.cpp

522

Write32(OUT, EVERGREEN_HDP_NONSURFACE_BASE, (gInfo->fb.vramStart >> 8));

src/add-ons/accelerants/radeon_hd/gpu.cpp

523

Write32(OUT, EVERGREEN_HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));

src/add-ons/accelerants/radeon_hd/gpu.cpp

524

Write32(OUT, EVERGREEN_HDP_NONSURFACE_SIZE, 0x3FFFFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

531

Write32(OUT, EVERGREEN_MC_VM_AGP_BASE, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

532

Write32(OUT, EVERGREEN_MC_VM_AGP_TOP, 0x0FFFFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

533

Write32(OUT, EVERGREEN_MC_VM_AGP_BOT, 0x0FFFFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

541

Write32(OUT, 0x000300, Read32(OUT, 0x000300) & 0xFFFCFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

647

Write32(OUT, GRBM_SOFT_RESET, RADEON_SOFT_RESET_CP);

src/add-ons/accelerants/radeon_hd/gpu.cpp

650

Write32(OUT, GRBM_SOFT_RESET, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

659

Write32(OUT, CP_RB_CNTL, controlScratch);

src/add-ons/accelerants/radeon_hd/gpu.cpp

662

Write32(OUT, CP_SEM_WAIT_TIMER, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

663

Write32(OUT, CP_RB_WPTR_DELAY, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

667

Write32(OUT, CP_RB_CNTL, controlScratch);

src/add-ons/accelerants/radeon_hd/gpu.cpp

670

Write32(OUT, CP_RB_RPTR_WR, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

671

Write32(OUT, CP_RB_WPTR, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

687

Write32(OUT, CP_RB_RPTR_ADDR, (ringPointer & 0xfffffffc));

src/add-ons/accelerants/radeon_hd/gpu.cpp

688

Write32(OUT, CP_RB_RPTR_ADDR_HI, upper_32_bits(ringPointer));

src/add-ons/accelerants/radeon_hd/gpu.cpp

692

Write32(OUT, CP_RB_CNTL, controlScratch);

src/add-ons/accelerants/radeon_hd/gpu.cpp

713

Write32(OUT, CP_RB_BASE, commandPointer >> 8);

src/add-ons/accelerants/radeon_hd/gpu.cpp

714

Write32(OUT, CP_ME_CNTL, 0xff);

src/add-ons/accelerants/radeon_hd/gpu.cpp

715

Write32(OUT, CP_DEBUG, (1 << 27) | (1 << 28));

src/add-ons/accelerants/radeon_hd/gpu.cpp

729

Write32(OUT, R600_SCRATCH_ADDR, (uint32)scratchAddr);

src/add-ons/accelerants/radeon_hd/gpu.cpp

731

Write32(OUT, R600_SCRATCH_UMSK, 0x7);

src/add-ons/accelerants/radeon_hd/gpu.cpp

739

Write32(OUT, R600_LAST_FRAME_REG, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

742

Write32(OUT, R600_LAST_DISPATCH_REG, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

745

Write32(OUT, R600_LAST_CLEAR_REG, 0);

src/add-ons/accelerants/radeon_hd/gpu.cpp

781

Write32(OUT, EVERGREEN_P1PLL_SS_CNTL, ssControl);

src/add-ons/accelerants/radeon_hd/gpu.cpp

790

Write32(OUT, EVERGREEN_P2PLL_SS_CNTL, ssControl);

src/add-ons/accelerants/radeon_hd/gpu.cpp

804

Write32(OUT, AVIVO_P1PLL_INT_SS_CNTL, ssControl);

src/add-ons/accelerants/radeon_hd/gpu.cpp

813

Write32(OUT, AVIVO_P2PLL_INT_SS_CNTL, ssControl);

src/add-ons/accelerants/radeon_hd/mode.cpp

477

Write32(OUT, backlightReg, level);

src/add-ons/kernel/drivers/audio/ac97/geode/driver.h

160

void Write32(uint32 reg, uint32 value)

src/add-ons/kernel/drivers/audio/ac97/geode/driver.h

162

controller->Write32(ACC_BM0_CMD + offset + reg, value);

src/add-ons/kernel/drivers/audio/ac97/geode/driver.h

93

void Write32(uint32 reg, uint32 value)

src/add-ons/kernel/drivers/audio/ac97/geode/geode_controller.cpp

157

controller->Write32(ACC_CODEC_CNTL, ACC_CODEC_CNTL_LNK_WRM_RST

src/add-ons/kernel/drivers/audio/ac97/geode/geode_controller.cpp

382

stream->Write32(STREAM_PRD, stream->physical_buffer_descriptors);

src/add-ons/kernel/drivers/audio/ac97/geode/geode_controller.cpp

56

controller->Write32(ACC_CODEC_CNTL,

src/add-ons/kernel/drivers/audio/ac97/geode/geode_controller.cpp

88

controller->Write32(ACC_CODEC_CNTL,

src/add-ons/kernel/drivers/audio/hda/driver.h

114

void Write32(uint32 reg, uint32 value)

src/add-ons/kernel/drivers/audio/hda/driver.h

140

Write32(reg, temp);

src/add-ons/kernel/drivers/audio/hda/driver.h

212

void Write32(uint32 reg, uint32 value)

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

1149

controller->Write32(HDAC_INTR_CONTROL, 0);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

1286

controller->Write32(HDAC_INTR_CONTROL, INTR_CONTROL_GLOBAL_ENABLE

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

1335

controller->Write32(HDAC_INTR_CONTROL, 0);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

1398

controller->Write32(HDAC_INTR_CONTROL, 0);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

451

controller->Write32(HDAC_INTR_CONTROL, 0);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

487

controller->Write32(HDAC_DMA_POSITION_BASE_LOWER, 0);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

488

controller->Write32(HDAC_DMA_POSITION_BASE_UPPER, 0);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

494

controller->Write32(HDAC_GLOBAL_CONTROL, control & ~GLOBAL_CONTROL_RESET);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

507

controller->Write32(HDAC_GLOBAL_CONTROL, control | GLOBAL_CONTROL_RESET);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

520

controller->Write32(HDAC_GLOBAL_CONTROL,

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

608

controller->Write32(HDAC_CORB_BASE_LOWER, (uint32)pe.address);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

610

controller->Write32(HDAC_CORB_BASE_UPPER,

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

614

controller->Write32(HDAC_RIRB_BASE_LOWER, (uint32)pe.address + rirbOffset);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

616

controller->Write32(HDAC_RIRB_BASE_UPPER,

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

621

controller->Write32(HDAC_DMA_POSITION_BASE_LOWER,

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

624

controller->Write32(HDAC_DMA_POSITION_BASE_UPPER,

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

769

controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL)

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

795

controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL)

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

972

stream->Write32(HDAC_STREAM_BUFFERS_BASE_LOWER,

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

975

stream->Write32(HDAC_STREAM_BUFFERS_BASE_UPPER,

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

981

stream->Write32(HDAC_STREAM_BUFFER_SIZE, stream->buffer_size

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

985

stream->controller->Write32(HDAC_DMA_POSITION_BASE_LOWER,