WRITE_IB_REG
WRITE_IB_REG( RADEON_RB3D_CNTL, 0 );
WRITE_IB_REG( RADEON_DEFAULT_OFFSET, pitch_offset );
WRITE_IB_REG( RADEON_DST_PITCH_OFFSET, pitch_offset );
WRITE_IB_REG( RADEON_SRC_PITCH_OFFSET, pitch_offset );
WRITE_IB_REG( RADEON_DEFAULT_SC_BOTTOM_RIGHT,
WRITE_IB_REG( RADEON_DP_GUI_MASTER_CNTL,
WRITE_IB_REG( RADEON_DP_BRUSH_FRGD_CLR, 0xffffffff);
WRITE_IB_REG( RADEON_DP_BRUSH_BKGD_CLR, 0x00000000);
WRITE_IB_REG( RADEON_DP_SRC_FRGD_CLR, 0xffffffff);
WRITE_IB_REG( RADEON_DP_SRC_BKGD_CLR, 0x00000000);
WRITE_IB_REG( RADEON_DP_WRITE_MASK, 0xffffffff);
WRITE_IB_REG( RADEON_RB2D_DSTCACHE_CTLSTAT, RADEON_RB2D_DC_FLUSH_ALL );
WRITE_IB_REG( RADEON_WAIT_UNTIL, RADEON_WAIT_2D_IDLECLEAN |
WRITE_IB_REG( RADEON_SCRATCH_REG0, ai->si->engine.count );
WRITE_IB_REG( RADEON_OV0_VID_BUF0_BASE_ADRS, offset);
WRITE_IB_REG( RADEON_OV0_AUTO_FLIP_CNTRL, si->overlay_mgr.auto_flip_reg );
WRITE_IB_REG( RADEON_DAC_CNTL2,
WRITE_IB_REG( RADEON_PALETTE_INDEX, 0 );
WRITE_IB_REG( RADEON_PALETTE_DATA, (i << 16) | (i << 8) | i );
WRITE_IB_REG( RADEON_DAC_CNTL2,
WRITE_IB_REG( RADEON_PALETTE_INDEX, first );
WRITE_IB_REG( RADEON_PALETTE_DATA,