WR4
WR4(sc, sc->sc_hwspecs.rxDescRead, sc->sc_hwdma.rxDescRead);
WR4(sc, sc->sc_hwspecs.rxDescWrite, sc->sc_hwdma.rxDescRead);
WR4(sc, sc->sc_hwspecs.wcbBase[i], sc->sc_hwdma.wcbBase[i]);
WR4(mh, MACREG_REG_PROMISCUOUS, ena ? v | 1 : v &~ 1);
WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, ISR_RESET);
WR4(mh, MACREG_REG_GEN_PTR, mh->mh_cmdaddr);
WR4(mh, MACREG_REG_INT_CODE, 0x00);
WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_DOOR_BELL);
WR4(mh, MACREG_REG_INT_CODE, 0);
WR4(mh, MACREG_REG_INT_CODE, 0);
WR4(mh, 0x00006014, 0x33);
WR4(mh, 0x00006018, 0xa3a2632);
WR4(mh, 0x00006010, SDRAMSIZE_Addr);
WR4(mh, MACREG_REG_A2H_INTERRUPT_CLEAR_SEL, MACREG_A2HRIC_BIT_MASK);
WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE, 0x00);
WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0x00);
WR4(mh, MACREG_REG_A2H_INTERRUPT_STATUS_MASK, MACREG_A2HRIC_BIT_MASK);
WR4(mh, MACREG_REG_INT_CODE, 0);
WR4(mh, MACREG_REG_GEN_PTR, OpMode);
WR4(mh, MACREG_REG_INT_CODE, 0x00);
WR4(mh, MACREG_REG_A2H_INTERRUPT_CAUSE,
WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, 0);
WR4(mh, MACREG_REG_A2H_INTERRUPT_MASK, mask);
WR4(mh, MACREG_REG_H2A_INTERRUPT_EVENTS, MACREG_H2ARIC_BIT_PPA_READY);