AXGE_ACCESS_MAC
axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CTCR, csum);
axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CRCR, csum);
link_status = axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PLSR);
axge_write_mem(sc, AXGE_ACCESS_MAC, 5, AXGE_RX_BULKIN_QCTRL, tmp, 5);
axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val);
axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, 0);
axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, EPPRCR_IPRL);
axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT,
axge_read_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,
val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR);
axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_EPPRCR, val);
axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_CLK_SELECT, 0);
axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, 0);
axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
axge_write_mem(sc, AXGE_ACCESS_MAC, 8, AXGE_MFA, (void *)&hashtbl, 8);
axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_RCR, rxmode);
axge_write_mem(sc, AXGE_ACCESS_MAC, ETHER_ADDR_LEN, AXGE_NIDR,
axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLLR, 0x34);
axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_PWLHR, 0x52);
axge_write_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR, 0);
(void)axge_read_cmd_1(sc, AXGE_ACCESS_MAC, AXGE_MMSR);
axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, MSR_GM | MSR_FD |
val = axge_read_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR);
axge_write_cmd_2(sc, AXGE_ACCESS_MAC, 2, AXGE_MSR, val);