AUICH_REG_X_CR
auich_reg_write_8(&stream->card->config, stream->base + AUICH_REG_X_CR, 0);
stream->base + AUICH_REG_X_CR, CR_RR);
stream->base + AUICH_REG_X_CR)) {
auich_reg_write_8(&stream->card->config, stream->base + AUICH_REG_X_CR, CR_RPBM | CR_LVBIE | CR_FEIE | CR_IOCE);
auich_reg_read_8(&stream->card->config, stream->base + AUICH_REG_X_CR);
auich_reg_write_8(&stream->card->config, stream->base + AUICH_REG_X_CR,
auich_reg_read_8(&stream->card->config, stream->base + AUICH_REG_X_CR) & ~CR_RPBM);
auich_reg_write_8(&stream->card->config, stream->base + AUICH_REG_X_CR, 0);
auich_reg_write_8(&stream->card->config, stream->base + AUICH_REG_X_CR, CR_RR);
if (0 == auich_reg_read_8(&stream->card->config, stream->base + AUICH_REG_X_CR)) {
LOG(("PI AUICH_REG_X_CR = %#x\n", auich_reg_read_8(config, AUICH_REG_X_CR + AUICH_REG_PI_BASE)));
LOG(("PO AUICH_REG_X_CR = %#x\n", auich_reg_read_8(config, AUICH_REG_X_CR + AUICH_REG_PO_BASE)));