SHOW_FLOW
SHOW_FLOW( 4, "colorIndex", colorIndex);
SHOW_FLOW( 3, "mark %d as being free", oldest_buffer->send_tag );
SHOW_FLOW( 3, "got %d", buffer_idx );
SHOW_FLOW( 3, "buffer_idx=%d, never_used=%d", buffer_idx, never_used );
SHOW_FLOW( 3, "@%d: %x", ring_tail, val ); \
SHOW_FLOW( 3, "buffer_idx=%d, buffer_size=%d, state_buffer_idx=%d, state_buffer_size=%d",
SHOW_FLOW( 3, "buffer has uneven size (%d)", buffer_size );
SHOW_FLOW( 3, "Assigned tag %d", cp->buffers.buffers[buffer_idx].send_tag );
SHOW_FLOW( 3, "head=%ld, tail=%ld, space=%ld",
SHOW_FLOW( 3, "processed_tag=%d", cur_processed_tag );
SHOW_FLOW( 3, "oldset buffer's tag: %d", oldest_buffer->send_tag );
SHOW_FLOW( 4, "got counter=%d", si->engine.count );
SHOW_FLOW( 4, "passed counter=%d",
SHOW_FLOW( 4, "CRTC %d, DVI %d", (crtc == &si->crtc[0]) ? 0 : 1, crtc->flatpanel_port );
SHOW_FLOW( 4, "X %d, virtX %d", target->timing.h_display, target->virtual_width);
SHOW_FLOW( 4, "fpRes %dx%d", flatpanel->panel_xres, flatpanel->panel_yres);
SHOW_FLOW( 4, "%ld, %ld not supported", dst->virtual_width, dst->virtual_height );
SHOW_FLOW( 4, "%ld, %ld", mode->virtual_width, mode->virtual_height );
SHOW_FLOW( 2, "H: %4d %4d %4d %4d (v=%4d)",
SHOW_FLOW( 2, "V: %4d %4d %4d %4d (h=%4d)",
SHOW_FLOW( 2, "clk: %ld", mode.timing.pixel_clock );
SHOW_FLOW( 2, "H: %4d %4d %4d %4d (v=%4d)",
SHOW_FLOW( 2, "V: %4d %4d %4d %4d (h=%4d)",
SHOW_FLOW( 2, "clk: %ld", target->timing.pixel_clock );
SHOW_FLOW( 0, "RADEON_DAC_CNTL %08X ", INREG( regs, RADEON_DAC_CNTL ));
SHOW_FLOW( 0, "RADEON_DAC_CNTL2 %08X ", INREG( regs, RADEON_DAC_CNTL2 ));
SHOW_FLOW( 0, "RADEON_TV_DAC_CNTL %08X ", INREG( regs, RADEON_TV_DAC_CNTL ));
SHOW_FLOW( 0, "RADEON_DISP_OUTPUT_CNTL %08X ", INREG( regs, RADEON_DISP_OUTPUT_CNTL ));
SHOW_FLOW( 0, "RADEON_AUX_SC_CNTL %08X ", INREG( regs, RADEON_AUX_SC_CNTL ));
SHOW_FLOW( 0, "RADEON_CRTC_EXT_CNTL %08X ", INREG( regs, RADEON_CRTC_EXT_CNTL ));
SHOW_FLOW( 0, "RADEON_CRTC_GEN_CNTL %08X ", INREG( regs, RADEON_CRTC_GEN_CNTL ));
SHOW_FLOW( 0, "RADEON_CRTC2_GEN_CNTL %08X ", INREG( regs, RADEON_CRTC2_GEN_CNTL ));
SHOW_FLOW( 0, "RADEON_DISP_MISC_CNTL %08X ", INREG( regs, RADEON_DISP_MISC_CNTL ));
SHOW_FLOW( 0, "RADEON_FP_GEN_CNTL %08X ", INREG( regs, RADEON_FP_GEN_CNTL ));
SHOW_FLOW( 0, "RADEON_FP2_GEN_CNTL %08X ", INREG( regs, RADEON_FP2_GEN_CNTL ));
SHOW_FLOW( 0, "RADEON_LVDS_GEN_CNTL %08X ", INREG( regs, RADEON_LVDS_GEN_CNTL ));
SHOW_FLOW( 0, "RADEON_TMDS_PLL_CNTL %08X ", INREG( regs, RADEON_TMDS_PLL_CNTL ));
SHOW_FLOW( 0, "RADEON_TMDS_TRANSMITTER_CNTL %08X ", INREG( regs, RADEON_TMDS_TRANSMITTER_CNTL ));
SHOW_FLOW( 0, "RADEON_FP_H_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_H_SYNC_STRT_WID ));
SHOW_FLOW( 0, "RADEON_FP_V_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_V_SYNC_STRT_WID ));
SHOW_FLOW( 0, "RADEON_FP_H2_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_H2_SYNC_STRT_WID ));
SHOW_FLOW( 0, "RADEON_FP_V2_SYNC_STRT_WID %08X ", INREG( regs, RADEON_FP_V2_SYNC_STRT_WID ));
SHOW_FLOW( 2, "width=%d, height=%d", mode.timing.h_display, mode.timing.v_display );
SHOW_FLOW( 2, "independant heads: %d, different heads: %d",
SHOW_FLOW( 2, "scrolling %s", vc->scroll ? "enabled" : "disabled" );
SHOW_FLOW( 0, "frame buffer CPU-address=%x, phys-address=%x",
SHOW_FLOW( 2, "SetModes 1=%s, 2=%s",
SHOW_FLOW( 3, "pitch=%ld", vc->pitch );
SHOW_FLOW( 2, "crtc_pitch=%ld", values->crtc_pitch );
SHOW_FLOW( 3, "Setting address %x on port %d",
SHOW_FLOW( 4, "h_display_start=%ld, v_display_start=%ld",
SHOW_FLOW( 2, "before: fp_gen_cntl=%08lx, horz=%08lx, vert=%08lx, lvds_gen_cntl=%08lx",
SHOW_FLOW( 2, "after: fp_gen_cntl=%08lx, fp2_gen_cntl=%08lx, horz=%08lx, vert=%08lx, lvds_gen_cntl=%08lx",
SHOW_FLOW( 2, "Restart in frame %d, line %d, pixel %d",
SHOW_FLOW( 3, "flicker removal=%d", flicker_removal );
SHOW_FLOW( 3, "%d < %d ?",
SHOW_FLOW( 2, "internal_encoder=%s, format=%d",
SHOW_FLOW( 3, "lines_before_active=%d, start_line=%d", lines_before_active, start_line );
SHOW_FLOW( 3, "uv_inc=%d", params->uv_inc );
SHOW_FLOW( 3, "f_first=%d, v_first=%d, h_first=%d", f_first, v_first, h_first );
SHOW_FLOW( 2, "tv_master_cntl=%x", values->tv_master_cntl );
SHOW_FLOW( 3, "first_num=%d", first_num );
SHOW_FLOW( 3, "time_to_active=%d, crt_freq=%d, tv_freq=%d",
SHOW_FLOW( 3, "restart_to_first_active_pixel_to_FIFO=%d", restart_to_first_active_pixel_to_FIFO );
SHOW_FLOW( 3, "after delay compensation first_num=%d", first_num );
SHOW_FLOW(2, "Found detailed timing for mode %dx%d in DDC data",
SHOW_FLOW(2, "Unsupported standard mode %dx%d@%dHz (not VESA)",
SHOW_FLOW(2, "Found DDC data for standard mode %dx%d",
SHOW_FLOW(2, "Found DDC-capable monitor @0x%04x", ddcPort);
SHOW_FLOW(2, "Edid Data for CRTC %d on line %d", i, routes->port_info[i].ddc_type);
SHOW_FLOW(2, "No Edid Pin Assigned to CRTC %d ", i);
SHOW_FLOW( 2, "display_devices=%x, whished_num_heads=%d",
SHOW_FLOW( 2, "after restriction: %x", display_devices );
SHOW_FLOW( 2, "CRTC1: 0x%x, CRTC2: 0x%x", crtc1_displays, crtc2_displays );
SHOW_FLOW( 2, "display_devices=%x, whished_num_heads=%d, use_laptop_panel=%d",
SHOW_FLOW( 2, "num_crtc: %d, CRTC1 (%s): 0x%x, CRTC2 (%s): 0x%x",
SHOW_FLOW( 3, "relative position of second screen: %d, %d", x, y );
SHOW_FLOW( 1, "set tv_standard (internal %d, public %d)",
SHOW_FLOW( 3, "area0=%d, area1=%d", area0, area1 );
SHOW_FLOW( 3, "key=%lx", res );
SHOW_FLOW( 3, "p1_4tap_allowed=%d, p23_4t_allowed=%d",
SHOW_FLOW( 3, "group_size=%d, p1_step_by=%d, p23_step_by=%d",
SHOW_FLOW( 3, "ow: h=%d, v=%d, width=%d, height=%d",
SHOW_FLOW( 3, "offset_left=%d, offset_right=%d, offset_top=%d, offset_bottom=%d",
SHOW_FLOW( 3, "mode: w=%d, h=%d",
SHOW_FLOW( 3, "src=(%d, %d, %d, %d)",
SHOW_FLOW( 3, "dest=(%d, %d, %d, %d)",
SHOW_FLOW( 3, "ati_space=%d", node->ati_space );
SHOW_FLOW( 3, "p1_h_inc=%x, p23_h_inc=%x", p1_h_inc, p23_h_inc );
SHOW_FLOW( 3, "p1_x_start=%d, p1_x_end=%d", p1_x_start, p1_x_end );
SHOW_FLOW( 3, "p23_x_start=%d, p23_x_end=%d", p23_x_start, p23_x_end );
SHOW_FLOW( 3, "rel_offset=%x", si->active_overlay.rel_offset );
SHOW_FLOW( 3, "p1_active_lines=%d, p23_active_lines=%d",
SHOW_FLOW( 3, "v_inc=%x", v_inc );
SHOW_FLOW( 3, "p1_h_accum_init=%x", tmp );
SHOW_FLOW( 3, "p23_h_accum_init=%x", tmp );
SHOW_FLOW( 3, "p1_v_accum_init=%x", tmp );
SHOW_FLOW( 3, "p23_v_accum_init=%x", tmp );
SHOW_FLOW(4, "What overlay format is this??? %d", node->ati_space);
SHOW_FLOW( 3, "Unsupported format (%x)", (int)cs );
SHOW_FLOW( 0, "success: mem_handle=%x, offset=%x, CPU-address=%x, phys-address=%x",
SHOW_FLOW( 3, "ups - couldn't free memory (handle=%x, status=%s)",
SHOW_FLOW( 3, "first=%d, count=%d", first, count );
SHOW_FLOW( 2, "fixed post divider: %d", fixed_post_div );
SHOW_FLOW( 2, "freq=%ld", mode->timing.pixel_clock );
SHOW_FLOW( 2, "dot_clock_freq=%ld, pll_output_freq=%ld, ref_div=%d, feedback_div=%d, post_div=%d",
SHOW_FLOW( 3, "Bus has %d slots", bus->left_slots );
SHOW_FLOW(4, "path_id=%d", bus->path_id);
SHOW_FLOW(3, "bus = %p", bus);
SHOW_FLOW(3, "path=%d", ccb->path_id);
SHOW_FLOW(3, "%d:%d:%d", bus->path_id, target_id, target_lun);
SHOW_FLOW(3, "initiator_id=%d", initiator_id);
SHOW_FLOW(3, "target: %d", target_id);
SHOW_FLOW(3, "lun: %d", lun);
SHOW_FLOW( 3, "status=%x", worker_req->subsys_status );
SHOW_FLOW(3, "%p", node);
SHOW_FLOW(1, "to_buffer=%d, %" B_PRIu32 " bytes", to_buffer, size);
SHOW_FLOW(1, "count=%" B_PRIu32, sg_list_count);
SHOW_FLOW(1, "addr=%" B_PRIxPHYSADDR ", size=%" B_PRIuPHYSADDR,
SHOW_FLOW(1, "Buffering finished, %x, %" B_PRIx32,
SHOW_FLOW(0, "S/G-entry crosses DMA boundary @%" B_PRIxPHYSADDR,
SHOW_FLOW(0, "S/G-entry has bad alignment @%#" B_PRIxPHYSADDR,
SHOW_FLOW(0, "end of S/G-entry has bad alignment @%" B_PRIxPHYSADDR,
SHOW_FLOW(0, "S/G-entry above high address @%" B_PRIxPHYSADDR,
SHOW_FLOW(0, "S/G-entry is too long (%" B_PRIuPHYSADDR "/%" B_PRIu32
SHOW_FLOW(3, "bus=%p, dpc=%p", bus, dpc);
SHOW_FLOW(3, "bus=%p, dpc_list=%p", bus, bus->dpc_list);
SHOW_FLOW(3, "allocation_length=%" B_PRIuSIZE, allocationLength);
SHOW_FLOW(3, "param_list_length=%ld", param_list_length_6);
SHOW_FLOW(3, "command=%x", request->cdb[0]);
SHOW_FLOW(0, "fixing MODE SENSE(6) (%d bytes)", transfer_size_6);
SHOW_FLOW(3, "ANSI version: %d, response data format: %d",
SHOW_FLOW( 3, "sense_key=%d, sense_asc=%d", sense_key, sense_asc );
SHOW_FLOW(3, "offset=%u, req_size_limit=%d, size=%d, sg_list=%p, sg_count=%d, %s buffer",
SHOW_FLOW(0, "buffer = %p, virt_addr = %#" B_PRIxPHYSADDR ", bytes = %"
SHOW_FLOW(3, "physical = %#" B_PRIxPHYSADDR ", address = %p",
SHOW_FLOW( 1, "inserting after %p (pos=%" B_PRId64 ") and before %p (pos=%" B_PRId64 ")",
SHOW_FLOW( 3, "inserting new_request=%p, pos=%" B_PRId64, new_request,
SHOW_FLOW( 3, "first=%p, pos=%" B_PRId64 ", last_pos=%" B_PRId64,
SHOW_FLOW( 3, "request=%p", request );
SHOW_FLOW( 3, "request=%p", request );
SHOW_FLOW( 3, "request=%p", request );
SHOW_FLOW(3, "ccb=%p, data=%p, data_length=%" B_PRIu32, ccb, ccb->data,
SHOW_FLOW(3, "ccb=%p, data=%p, data_length=%" B_PRId32,
SHOW_FLOW(3, "Checking violation of dma boundary 0x%" B_PRIx32
SHOW_FLOW(4, "addr=%#" B_PRIxPHYSADDR ", size=%" B_PRIxPHYSADDR
SHOW_FLOW(3, "Got sense: %d bytes", sense_len);
SHOW_FLOW(3, "%p", request);
SHOW_FLOW(3, "subsys=%x, device=%x, flags=%" B_PRIx32
SHOW_FLOW(1, "%" B_PRId64, device->last_sort);
SHOW_FLOW(3, "ordered=%d", request->ordered);
SHOW_FLOW(1, "%" B_PRId64, device->last_sort);
SHOW_FLOW( 3, "num_entries=%" B_PRIu32 ", mapped_len=%" B_PRIxSIZE,
SHOW_FLOW(3, "vec_count=%" B_PRIuSIZE ", vec_offset=%" B_PRIuSIZE ", len=%"
SHOW_FLOW( 3, "left_len=%d, vec_count=%d, cur_idx=%" B_PRIu32,
SHOW_FLOW( 3, "range_start=%" B_PRIxADDR ", range_len=%" B_PRIxSIZE,
SHOW_FLOW( 3, "cur_num_entries=%" B_PRIu32 ", cur_mapped_len=%x",
SHOW_FLOW(4, "%x: %s", op, strerror(res));
SHOW_FLOW(3, "name=%s", name);
SHOW_FLOW(3, "1: %d - %d", volume->port0_channel, volume->port0_volume);
SHOW_FLOW(3, "2: %d - %d", volume->port1_channel, volume->port1_volume);
SHOW_FLOW(3, "3: %d - %d", volume->port2_channel, volume->port2_volume);
SHOW_FLOW(3, "4: %d - %d", volume->port3_channel, volume->port3_volume);
SHOW_FLOW( 3, "bus_cntl=%" B_PRIx32, INREG( di->regs, RADEON_BUS_CNTL ));
SHOW_FLOW( 0, "%d", cp->buffers.oldest );
SHOW_FLOW( 3, "aligned_phys=%p", aligned_phys );
SHOW_FLOW( 2, "h_total=%d, h_disp=%d", a * 8, b * 8 );
SHOW_FLOW( 2, "v_total=%d, v_disp=%d", a, b );
SHOW_FLOW( 2, "h_total=%d, h_disp=%d", a * 8, b * 8 );
SHOW_FLOW( 2, "v_total=%d, v_disp=%d", a, b );
SHOW_FLOW(3, "making /dev/%s", di->name);
SHOW_FLOW( 3, "name=%s, flags=%" B_PRIu32 ", cookie=%p", name, flags, cookie);
SHOW_FLOW(3, "returning 0x%08" B_PRIx32, result);
SHOW_FLOW( 3, "mapped frame buffer @%p", si->local_mem );
SHOW_FLOW( 3, "device: %02X%02X%02X",
SHOW_FLOW( 3, "old PCI command state: 0x%08" B_PRIx32, tmp );
SHOW_FLOW( 2, "address=%" B_PRIx32 ", count=%" B_PRIu32 " ",
SHOW_FLOW( 2, "address=%" B_PRIx32 ", count=%" B_PRIu32 ", ",
SHOW_FLOW( 2 ,"cannot write %x to VIPH_REG_ADDR\n",
SHOW_FLOW( 2, "count %" B_PRIu32, count);
SHOW_FLOW( 3, "No device found on channel %d", channel);
SHOW_FLOW( 3, "Device %08" B_PRIx32 " found on channel %d",
SHOW_FLOW(3, "%x", (int)val);
SHOW_FLOW( 4, "%#010" B_PRIx32 ", %" B_PRIu16 ", %d",
SHOW_FLOW(3, "virt=%p, phys=%x", channel->prdt, (int)channel->prdt_phys);
SHOW_FLOW( 4, "%x->HI(%x)", tf->raw.r[i + 7], i );
SHOW_FLOW( 4, "%x->LO(%x)", tf->raw.r[i], i );
SHOW_FLOW( 4, "%x: %x", i, (int)tf->raw.r[i] );
SHOW_FLOW(3, "%p, %p", device, request);
SHOW_FLOW(3, "capacity = %" B_PRIu64 ", block_size = %" B_PRIu32
SHOW_FLOW(3, "TRIM: Block limits: size = %" B_PRIu32
SHOW_FLOW(3, "done (%s)", strerror(res));
SHOW_FLOW(3, "UNMAP data used %" B_PRIu16
SHOW_FLOW(3, "%d", request->device_status & SCSI_STATUS_MASK);
SHOW_FLOW(4, "%d", request->subsys_status & SCSI_SUBSYS_STATUS_MASK);
SHOW_FLOW(3, "flag=%x, next_tag=%x, ordered: %s",
SHOW_FLOW(2, "%s", strerror(status));
SHOW_FLOW( 3, "action: %x, error: %x", (int)res.action, (int)res.error_code);
SHOW_FLOW(3, "error_code: %x", (int)res.error_code);