headers/private/kernel/arch/riscv64/arch_uart_sifive.h

91

Regs();

src/system/boot/platform/riscv/devices.cpp

44

return (*(uint32*)(&fBlockIo->Regs()->config[0])

src/system/boot/platform/riscv/devices.cpp

45

+ ((uint64)(*(uint32*)(&fBlockIo->Regs()->config[4])) << 32)

src/system/boot/platform/riscv/virtio.cpp

267

dev->Regs()->status = 0; // reset

src/system/boot/platform/riscv/virtio.h

61

inline VirtioRegs* volatile Regs() {return fRegs;}

src/system/kernel/arch/riscv64/arch_uart_sifive.cpp

49

Regs()->div = 0;

src/system/kernel/arch/riscv64/arch_uart_sifive.cpp

51

Regs()->div = (uint32)(quotient - 1);

src/system/kernel/arch/riscv64/arch_uart_sifive.cpp

80

while (Regs()->txdata.isFull) {}

src/system/kernel/arch/riscv64/arch_uart_sifive.cpp

81

Regs()->txdata.val = ch;

src/system/kernel/arch/riscv64/arch_uart_sifive.cpp

91

data.val = Regs()->rxdata.val;