src/add-ons/accelerants/radeon_hd/bios.cpp

103

reg = Read32(OUT, RADEON_CRTC_GEN_CNTL)

src/add-ons/accelerants/radeon_hd/bios.cpp

104

| Read32(OUT, RADEON_CRTC2_GEN_CNTL);

src/add-ons/accelerants/radeon_hd/bios.cpp

111

reg = Read32(OUT, R600_CONFIG_MEMSIZE);

src/add-ons/accelerants/radeon_hd/bios.cpp

113

reg = Read32(OUT, RADEON_CONFIG_MEMSIZE);

src/add-ons/accelerants/radeon_hd/bios.cpp

40

biosScratch2 = Read32(OUT, R600_SCRATCH_REG2);

src/add-ons/accelerants/radeon_hd/bios.cpp

41

biosScratch6 = Read32(OUT, R600_SCRATCH_REG6);

src/add-ons/accelerants/radeon_hd/bios.cpp

43

biosScratch2 = Read32(OUT, RADEON_BIOS_2_SCRATCH);

src/add-ons/accelerants/radeon_hd/bios.cpp

44

biosScratch6 = Read32(OUT, RADEON_BIOS_6_SCRATCH);

src/add-ons/accelerants/radeon_hd/bios.cpp

72

reg = Read32(OUT, EVERGREEN_CRTC_CONTROL

src/add-ons/accelerants/radeon_hd/bios.cpp

74

| Read32(OUT, EVERGREEN_CRTC_CONTROL

src/add-ons/accelerants/radeon_hd/bios.cpp

80

reg = Read32(OUT, EVERGREEN_CRTC_CONTROL

src/add-ons/accelerants/radeon_hd/bios.cpp

82

| Read32(OUT, EVERGREEN_CRTC_CONTROL

src/add-ons/accelerants/radeon_hd/bios.cpp

84

| Read32(OUT, EVERGREEN_CRTC_CONTROL

src/add-ons/accelerants/radeon_hd/bios.cpp

86

| Read32(OUT, EVERGREEN_CRTC_CONTROL

src/add-ons/accelerants/radeon_hd/bios.cpp

88

| Read32(OUT, EVERGREEN_CRTC_CONTROL

src/add-ons/accelerants/radeon_hd/bios.cpp

90

| Read32(OUT, EVERGREEN_CRTC_CONTROL

src/add-ons/accelerants/radeon_hd/bios.cpp

96

reg = Read32(OUT, AVIVO_D1CRTC_CONTROL)

src/add-ons/accelerants/radeon_hd/bios.cpp

97

| Read32(OUT, AVIVO_D2CRTC_CONTROL);

src/add-ons/accelerants/radeon_hd/connector.cpp

106

uint32 scl = Read32(OUT, info->i2c.sclEnReg) & ~info->i2c.sclEnMask;

src/add-ons/accelerants/radeon_hd/connector.cpp

109

Read32(OUT, info->i2c.sclEnReg);

src/add-ons/accelerants/radeon_hd/connector.cpp

111

uint32 sda = Read32(OUT, info->i2c.sdaEnReg) & ~info->i2c.sdaEnMask;

src/add-ons/accelerants/radeon_hd/connector.cpp

114

Read32(OUT, info->i2c.sdaEnReg);

src/add-ons/accelerants/radeon_hd/connector.cpp

46

buffer = Read32(OUT, info->i2c.sclMaskReg);

src/add-ons/accelerants/radeon_hd/connector.cpp

52

buffer = Read32(OUT, info->i2c.sclAReg) & ~info->i2c.sclAMask;

src/add-ons/accelerants/radeon_hd/connector.cpp

54

buffer = Read32(OUT, info->i2c.sdaAReg) & ~info->i2c.sdaAMask;

src/add-ons/accelerants/radeon_hd/connector.cpp

59

buffer = Read32(OUT, info->i2c.sclEnReg) & ~info->i2c.sclEnMask;

src/add-ons/accelerants/radeon_hd/connector.cpp

61

buffer = Read32(OUT, info->i2c.sdaEnReg) & ~info->i2c.sdaEnMask;

src/add-ons/accelerants/radeon_hd/connector.cpp

65

buffer = Read32(OUT, info->i2c.sclMaskReg);

src/add-ons/accelerants/radeon_hd/connector.cpp

72

Read32(OUT, info->i2c.sclMaskReg);

src/add-ons/accelerants/radeon_hd/connector.cpp

75

buffer = Read32(OUT, info->i2c.sdaMaskReg);

src/add-ons/accelerants/radeon_hd/connector.cpp

82

Read32(OUT, info->i2c.sdaMaskReg);

src/add-ons/accelerants/radeon_hd/connector.cpp

91

uint32 scl = Read32(OUT, info->i2c.sclYReg) & info->i2c.sclYMask;

src/add-ons/accelerants/radeon_hd/connector.cpp

92

uint32 sda = Read32(OUT, info->i2c.sdaYReg) & info->i2c.sdaYMask;

src/add-ons/accelerants/radeon_hd/display.cpp

878

= Read32(OUT, EVERGREEN_GRPH_FLIP_CONTROL + regs->crtcOffset);

src/add-ons/accelerants/radeon_hd/display.cpp

886

uint32 tmp = Read32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset);

src/add-ons/accelerants/radeon_hd/encoder.cpp

1185

uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);

src/add-ons/accelerants/radeon_hd/encoder.cpp

1195

uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);

src/add-ons/accelerants/radeon_hd/encoder.cpp

1207

uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);

src/add-ons/accelerants/radeon_hd/encoder.cpp

1219

uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);

src/add-ons/accelerants/radeon_hd/encoder.cpp

1248

uint32 biosScratch0 = Read32(OUT, R600_SCRATCH_REG0);

src/add-ons/accelerants/radeon_hd/encoder.cpp

1776

uint32 biosScratch3 = Read32(OUT, R600_SCRATCH_REG3);

src/add-ons/accelerants/radeon_hd/encoder.cpp

1825

uint32 biosScratch2 = Read32(OUT, R600_SCRATCH_REG2);

src/add-ons/accelerants/radeon_hd/encoder.cpp

2111

uint32 biosScratch6 = Read32(OUT, R600_SCRATCH_REG6);

src/add-ons/accelerants/radeon_hd/gpu.cpp

100

if ((Read32(OUT, GRBM_STATUS) & GUI_ACTIVE) == 0)

src/add-ons/accelerants/radeon_hd/gpu.cpp

160

if ((Read32(OUT, GRBM_STATUS) & grbmBusyMask) != 0

src/add-ons/accelerants/radeon_hd/gpu.cpp

161

|| (Read32(OUT, GRBM_STATUS2) & grbm2BusyMask) != 0) {

src/add-ons/accelerants/radeon_hd/gpu.cpp

176

Read32(OUT, GRBM_SOFT_RESET);

src/add-ons/accelerants/radeon_hd/gpu.cpp

184

Read32(OUT, GRBM_SOFT_RESET);

src/add-ons/accelerants/radeon_hd/gpu.cpp

212

Read32(OUT, GRBM_SOFT_RESET);

src/add-ons/accelerants/radeon_hd/gpu.cpp

216

Read32(OUT, GRBM_SOFT_RESET);

src/add-ons/accelerants/radeon_hd/gpu.cpp

273

gpuState->d1vgaControl = Read32(OUT, AVIVO_D1VGA_CONTROL);

src/add-ons/accelerants/radeon_hd/gpu.cpp

274

gpuState->d2vgaControl = Read32(OUT, AVIVO_D2VGA_CONTROL);

src/add-ons/accelerants/radeon_hd/gpu.cpp

275

gpuState->vgaRenderControl = Read32(OUT, AVIVO_VGA_RENDER_CONTROL);

src/add-ons/accelerants/radeon_hd/gpu.cpp

276

gpuState->vgaHdpControl = Read32(OUT, AVIVO_VGA_HDP_CONTROL);

src/add-ons/accelerants/radeon_hd/gpu.cpp

277

gpuState->d1crtcControl = Read32(OUT, AVIVO_D1CRTC_CONTROL);

src/add-ons/accelerants/radeon_hd/gpu.cpp

278

gpuState->d2crtcControl = Read32(OUT, AVIVO_D2CRTC_CONTROL);

src/add-ons/accelerants/radeon_hd/gpu.cpp

331

if (((idleStatus = Read32(MC, SRBM_STATUS)) & busyBits) == 0)

src/add-ons/accelerants/radeon_hd/gpu.cpp

408

Write32(OUT, 0x000300, Read32(OUT, 0x000300) & 0xFFFCFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

429

Read32(OUT, R700_HDP_DEBUG1);

src/add-ons/accelerants/radeon_hd/gpu.cpp

470

Write32(OUT, 0x000300, Read32(OUT, 0x000300) & 0xFFFCFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

511

uint32 tmp = Read32(OUT, EVERGREEN_MC_FUS_VM_FB_OFFSET)

src/add-ons/accelerants/radeon_hd/gpu.cpp

541

Write32(OUT, 0x000300, Read32(OUT, 0x000300) & 0xFFFCFFFF);

src/add-ons/accelerants/radeon_hd/gpu.cpp

568

vramBase = Read32(OUT, fbVMLocationReg) & 0xFFFF;

src/add-ons/accelerants/radeon_hd/gpu.cpp

648

Read32(OUT, GRBM_SOFT_RESET);

src/add-ons/accelerants/radeon_hd/gpu.cpp

723

uint64 scratchAddr = Read32(OUT, CP_RB_RPTR_ADDR) & 0xFFFFFFFC;

src/add-ons/accelerants/radeon_hd/gpu.cpp

724

scratchAddr |= ((uint64)Read32(OUT, CP_RB_RPTR_ADDR_HI)) << 32;

src/add-ons/accelerants/radeon_hd/gpu.cpp

776

ssControl = Read32(OUT, EVERGREEN_P1PLL_SS_CNTL);

src/add-ons/accelerants/radeon_hd/gpu.cpp

785

ssControl = Read32(OUT, EVERGREEN_P2PLL_SS_CNTL);

src/add-ons/accelerants/radeon_hd/gpu.cpp

799

ssControl = Read32(OUT, AVIVO_P1PLL_INT_SS_CNTL);

src/add-ons/accelerants/radeon_hd/gpu.cpp

808

ssControl = Read32(OUT, AVIVO_P2PLL_INT_SS_CNTL);

src/add-ons/accelerants/radeon_hd/mode.cpp

242

Read32(CRT, AVIVO_D1CRTC_STATUS));

src/add-ons/accelerants/radeon_hd/mode.cpp

244

Read32(CRT, AVIVO_D2CRTC_STATUS));

src/add-ons/accelerants/radeon_hd/mode.cpp

246

Read32(CRT, AVIVO_D1CRTC_CONTROL));

src/add-ons/accelerants/radeon_hd/mode.cpp

248

Read32(CRT, AVIVO_D2CRTC_CONTROL));

src/add-ons/accelerants/radeon_hd/mode.cpp

250

Read32(CRT, AVIVO_D1GRPH_ENABLE));

src/add-ons/accelerants/radeon_hd/mode.cpp

252

Read32(CRT, AVIVO_D2GRPH_ENABLE));

src/add-ons/accelerants/radeon_hd/mode.cpp

254

Read32(CRT, AVIVO_D1SCL_SCALER_ENABLE));

src/add-ons/accelerants/radeon_hd/mode.cpp

256

Read32(CRT, AVIVO_D2SCL_SCALER_ENABLE));

src/add-ons/accelerants/radeon_hd/mode.cpp

258

Read32(CRT, AVIVO_D1CRTC_BLANK_CONTROL));

src/add-ons/accelerants/radeon_hd/mode.cpp

260

Read32(CRT, AVIVO_D1CRTC_BLANK_CONTROL));

src/add-ons/accelerants/radeon_hd/mode.cpp

470

uint32_t level = Read32(OUT, backlightReg);

src/add-ons/accelerants/radeon_hd/mode.cpp

504

uint32_t backlightReg = Read32(OUT, radeon_get_backlight_register());

src/add-ons/kernel/drivers/audio/ac97/geode/driver.h

145

uint32 Read32(uint32 reg)

src/add-ons/kernel/drivers/audio/ac97/geode/driver.h

147

return controller->Read32(ACC_BM0_CMD + offset + reg);

src/add-ons/kernel/drivers/audio/ac97/geode/driver.h

78

uint32 Read32(uint32 reg)

src/add-ons/kernel/drivers/audio/ac97/geode/geode_controller.cpp

119

position = controller->Read32(ACC_BM0_PNTR + stream->dma_offset);

src/add-ons/kernel/drivers/audio/ac97/geode/geode_controller.cpp

43

&& (controller->Read32(ACC_CODEC_CNTL) & ACC_CODEC_CNTL_CMD_NEW); i--)

src/add-ons/kernel/drivers/audio/ac97/geode/geode_controller.cpp

67

v = controller->Read32(ACC_CODEC_STATUS);

src/add-ons/kernel/drivers/audio/hda/driver.h

137

uint32 temp = Read32(reg);

src/add-ons/kernel/drivers/audio/hda/driver.h

197

uint32 Read32(uint32 reg)

src/add-ons/kernel/drivers/audio/hda/driver.h

199

return controller->Read32(HDAC_STREAM_BASE + offset + reg);

src/add-ons/kernel/drivers/audio/hda/driver.h

99

uint32 Read32(uint32 reg)

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

207

value = base->Read32(reg);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

304

: stream->Read32(HDAC_STREAM_POSITION);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

309

uint32 linkBytePosition = stream->Read32(HDAC_STREAM_POSITION);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

355

uint32 intrStatus = controller->Read32(HDAC_INTR_STATUS);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

449

uint32 control = controller->Read32(HDAC_GLOBAL_CONTROL);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

490

control = controller->Read32(HDAC_GLOBAL_CONTROL);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

506

control = controller->Read32(HDAC_GLOBAL_CONTROL);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

519

control = controller->Read32(HDAC_GLOBAL_CONTROL);

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

769

controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL)

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

795

controller->Write32(HDAC_INTR_CONTROL, controller->Read32(HDAC_INTR_CONTROL)

src/add-ons/kernel/drivers/audio/hda/hda_controller.cpp

986

stream->controller->Read32(HDAC_DMA_POSITION_BASE_LOWER)

src/system/boot/platform/riscv/FwCfg.cpp

143

dprintf("fwCfgSelectSignature: 0x%08" B_PRIx32 "\n", Read32());

src/system/boot/platform/riscv/FwCfg.cpp

145

dprintf("fwCfgSelectId: : 0x%08" B_PRIx32 "\n", Read32());

src/system/boot/platform/riscv/FwCfg.cpp

73

uint32_t count = B_BENDIAN_TO_HOST_INT32(Read32());

src/system/boot/platform/riscv/FwCfg.cpp

94

uint32_t count = B_BENDIAN_TO_HOST_INT32(Read32());