Radeon_INPLL
uint32 Radeon_INPLL( vuint8 *regs, radeon_type asic, int addr );
old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL);
old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL);
Radeon_INPLL( ai->regs, ai->si->asic, mapping->address );
old_vclk_ecp_cntl = Radeon_INPLL(ai->regs, ai->si->asic,
values->pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL );
values->vclk_ecp_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL );
(Radeon_INPLL( regs, si->asic, RADEON_VCLK_ECP_CNTL) | (1<<18)));
if( (Radeon_INPLL( ai->regs, ai->si->asic, crtc_idx == 0 ? RADEON_PPLL_REF_DIV : RADEON_P2PLL_REF_DIV )
mclk_cntl = Radeon_INPLL( regs, di->asic, RADEON_MCLK_CNTL );
tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);
tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);
tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);
tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_MISC);
tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_MCLK_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
tmp = Radeon_INPLL(regs, asic, R300_SCLK_CNTL2);
tmp = Radeon_INPLL(regs, asic, RADEON_CLK_PWRMGT_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_CLK_PIN_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_SCLK_MORE_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_PLL_PWRMGT_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
uint32 tmp = Radeon_INPLL( regs, asic, addr );