READ_SPECIALREG
return READ_SPECIALREG(cntvct_el0);
return (READ_SPECIALREG(DAIF) & PSR_I) == 0;
return (Thread *)READ_SPECIALREG(tpidr_el1);
return READ_SPECIALREG(TTBR0_EL2); // TTBR1_EL2
return READ_SPECIALREG(TTBR0_EL2);
return READ_SPECIALREG(TTBR0_EL3);
return READ_SPECIALREG(SCTLR_EL1);
return READ_SPECIALREG(SCTLR_EL2);
return READ_SPECIALREG(SCTLR_EL3);
return READ_SPECIALREG(TCR_EL1);
return READ_SPECIALREG(TCR_EL2);
return READ_SPECIALREG(TCR_EL3);
return (READ_SPECIALREG(CurrentEL) >> 2);
return !(READ_SPECIALREG(PAR_EL1) & PAR_F);
return !(READ_SPECIALREG(PAR_EL1) & PAR_F);
return READ_SPECIALREG(TTBR1_EL1);
return READ_SPECIALREG(TTBR0_EL1);
uint64_t pa_size = READ_SPECIALREG(ID_AA64MMFR0_EL1) & ID_AA64MMFR0_PA_RANGE_MASK;
uint64 id_aa64mmfr1_el1 = READ_SPECIALREG(ID_AA64MMFR1_EL1);
uint64_t tcr = READ_SPECIALREG(TCR_EL1);
uint64_t mmfr1 = READ_SPECIALREG(ID_AA64MMFR1_EL1);
gCPU[curr_cpu].arch.mpidr = READ_SPECIALREG(MPIDR_EL1);
uint64_t asid = READ_SPECIALREG(TTBR0_EL1) >> 48;
ptPa = READ_SPECIALREG(TTBR1_EL1);
ptPa = READ_SPECIALREG(TTBR0_EL1);
sTimerTicksUS = READ_SPECIALREG(CNTFRQ_EL0) / 1000000;
phys_addr_t ptPa = READ_SPECIALREG(TTBR1_EL1) & kTtbrBasePhysAddrMask;
return (READ_SPECIALREG(PAR_EL1) & PAR_F) == 0;
return (READ_SPECIALREG(PAR_EL1) & PAR_F) == 0;
pt = READ_SPECIALREG(TTBR1_EL1) & kTtbrBasePhysAddrMask;
memset((void*) (KERNEL_PMAP_BASE + READ_SPECIALREG(TTBR0_EL1)), 0, B_PAGE_SIZE);
uint64_t mair = READ_SPECIALREG(MAIR_EL1);
uint64_t mmfr1 = READ_SPECIALREG(ID_AA64MMFR1_EL1);
uint64_t mmfr2 = READ_SPECIALREG(ID_AA64MMFR2_EL1);