REGS_NORTH_SHARED
#define INTEL_DISPLAY_A_PALETTE (0xa000 | REGS_NORTH_SHARED)
#define INTEL_DISPLAY_B_PALETTE (0xa800 | REGS_NORTH_SHARED)
#define INTEL_GEN9_CLKGATE_DIS_4 (0x653c | REGS_NORTH_SHARED)
#define INTEL_PWR_WELL_CTL_1_BIOS (0x5400 | REGS_NORTH_SHARED)
#define INTEL_PWR_WELL_CTL_2_DRIVER (0x5404 | REGS_NORTH_SHARED)
#define HSW_PWR_WELL_CTL3 (0x5408 | REGS_NORTH_SHARED)
#define HSW_PWR_WELL_CTL4 (0x540c | REGS_NORTH_SHARED)
#define ICL_PWR_WELL_CTL_AUX1 (0x5440 | REGS_NORTH_SHARED)
#define ICL_PWR_WELL_CTL_AUX2 (0x5444 | REGS_NORTH_SHARED)
#define ICL_PWR_WELL_CTL_AUX4 (0x544c | REGS_NORTH_SHARED)
#define ICL_PWR_WELL_CTL_DDI1 (0x5450 | REGS_NORTH_SHARED)
#define ICL_PWR_WELL_CTL_DDI2 (0x5454 | REGS_NORTH_SHARED)
#define ICL_PWR_WELL_CTL_DDI4 (0x545c | REGS_NORTH_SHARED)
#define INTEL_WRPLL_CTL_1_DPLL2 (0x6040 | REGS_NORTH_SHARED)
#define INTEL_WRPLL_CTL_2_DPLL3 (0x6060 | REGS_NORTH_SHARED)
#define PCH_BLC_PWM_CTL2 (0x8250 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL2
#define PCH_BLC_PWM_CTL (0x8254 | REGS_NORTH_SHARED) // Linux BLC_PWM_CPU_CTL
blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)]
blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)]
blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)]);