REGS_NORTH_PLANE_CONTROL
#define INTEL_PIPE_A_DATA_M (0x0050 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_PIPE_B_DATA_M (0x1050 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_PIPE_A_DATA_N (0x0054 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_PIPE_B_DATA_N (0x1054 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_PIPE_A_LINK_M (0x0060 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_PIPE_B_LINK_M (0x1060 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_PIPE_A_LINK_N (0x0064 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_PIPE_B_LINK_N (0x1064 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_C_PIPE_CONTROL (0x2008 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_A_PIPE_WATERMARK (0x5100 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_B_PIPE_WATERMARK (0x5104 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_C_PIPE_WATERMARK (0x5200 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_A_CONTROL (0x0180 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_A_BASE (0x0184 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_A_BYTES_PER_ROW (0x0188 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_A_POS (0x018c | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_A_IMAGE_SIZE (0x0190 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_A_SURFACE (0x019c | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_A_OFFSET_HAS (0x01a4 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_B_CONTROL (0x1180 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_B_BASE (0x1184 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_B_BYTES_PER_ROW (0x1188 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_B_POS (0x118c | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_B_IMAGE_SIZE (0x1190 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_B_SURFACE (0x119c | REGS_NORTH_PLANE_CONTROL)
#define INTEL_DISPLAY_B_OFFSET_HAS (0x11a4 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_CURSOR_CONTROL (0x0080 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_CURSOR_BASE (0x0084 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_CURSOR_POSITION (0x0088 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_CURSOR_PALETTE (0x0090 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_CURSOR_SIZE (0x00a0 | REGS_NORTH_PLANE_CONTROL)
#define INTEL_VGA_DISPLAY_CONTROL (0x1400 | REGS_NORTH_PLANE_CONTROL)
#define DDI_SKL_TRANS_CONF_A (0x0008 | REGS_NORTH_PLANE_CONTROL)
#define DDI_SKL_TRANS_CONF_B (0x1008 | REGS_NORTH_PLANE_CONTROL)
#define DDI_SKL_TRANS_CONF_C (0x2008 | REGS_NORTH_PLANE_CONTROL)
#define DDI_SKL_TRANS_CONF_EDP (0xf008 | REGS_NORTH_PLANE_CONTROL)
blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)]
blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)]
blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)]);