RADEON_VCLK_ECP_CNTL
RADEON_VCLK_ECP_CNTL);
Radeon_OUTPLL(ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL, value);
Radeon_OUTPLL(ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL,
values->vclk_ecp_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_VCLK_ECP_CNTL );
RADEON_VCLK_ECP_CNTL, values->vclk_ecp_cntl,
Radeon_OUTPLLP( regs, si->asic, RADEON_VCLK_ECP_CNTL,
Radeon_OUTPLL( regs, si->asic, RADEON_VCLK_ECP_CNTL,
(Radeon_INPLL( regs, si->asic, RADEON_VCLK_ECP_CNTL) | (1<<18)));
Radeon_OUTPLLP( regs, asic, crtc_idx == 0 ? RADEON_VCLK_ECP_CNTL : RADEON_PIXCLKS_CNTL,
crtc_idx == 0 ? RADEON_VCLK_ECP_CNTL : RADEON_PIXCLKS_CNTL,
tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);
tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);
tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);
tmp = Radeon_INPLL(regs, asic, RADEON_VCLK_ECP_CNTL);
Radeon_OUTPLL(regs, asic, RADEON_VCLK_ECP_CNTL, tmp);