RADEON_PIXCLKS_CNTL
old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL);
Radeon_OUTPLLP( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb );
Radeon_OUTPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, old_pixclks_cntl );
old_pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL);
Radeon_OUTPLLP( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb );
Radeon_OUTPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL, old_pixclks_cntl );
values->pixclks_cntl = Radeon_INPLL( ai->regs, ai->si->asic, RADEON_PIXCLKS_CNTL );
RADEON_PIXCLKS_CNTL, values->pixclks_cntl,
RADEON_PIXCLKS_CNTL, values->pixclks_cntl,
Radeon_OUTPLLP( regs, asic, crtc_idx == 0 ? RADEON_VCLK_ECP_CNTL : RADEON_PIXCLKS_CNTL,
crtc_idx == 0 ? RADEON_VCLK_ECP_CNTL : RADEON_PIXCLKS_CNTL,
tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);
tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);
tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);
tmp = Radeon_INPLL(regs, asic, RADEON_PIXCLKS_CNTL);
Radeon_OUTPLL(regs, asic, RADEON_PIXCLKS_CNTL, tmp);