src/add-ons/accelerants/radeon/Cursor.c

238

tmp = INREG( ai->regs, RADEON_CRTC2_GEN_CNTL );

src/add-ons/accelerants/radeon/Cursor.c

245

OUTREG( ai->regs, RADEON_CRTC2_GEN_CNTL, tmp );

src/add-ons/accelerants/radeon/SetDisplayMode.c

290

SHOW_FLOW( 0, "RADEON_CRTC2_GEN_CNTL %08X ", INREG( regs, RADEON_CRTC2_GEN_CNTL ));

src/add-ons/accelerants/radeon/crtc.c

38

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, values->crtc_gen_cntl,

src/add-ons/accelerants/radeon/dpms.c

176

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, 0,

src/add-ons/accelerants/radeon/dpms.c

180

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS),

src/add-ons/accelerants/radeon/dpms.c

184

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS),

src/add-ons/accelerants/radeon/dpms.c

188

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS),

src/add-ons/accelerants/radeon/dpms.c

246

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, 0, mask );

src/add-ons/accelerants/radeon/dpms.c

249

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), mask );

src/add-ons/accelerants/radeon/dpms.c

252

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), mask);

src/add-ons/accelerants/radeon/dpms.c

255

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL,

src/add-ons/accelerants/radeon/dpms.c

263

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, 0, ~RADEON_CRTC2_DISP_REQ_EN_B );

src/add-ons/accelerants/radeon/dpms.c

269

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_DISP_REQ_EN_B,

src/add-ons/accelerants/radeon/dpms.c

365

tmp = INREG( di->regs, RADEON_CRTC2_GEN_CNTL );

src/add-ons/accelerants/radeon/monitor_detection.c

185

old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

189

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

221

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, old_crtc2_gen_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

243

old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

252

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, value);

src/add-ons/accelerants/radeon/monitor_detection.c

281

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, old_crtc2_gen_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

350

old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

407

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, old_crtc2_gen_cntl);

src/add-ons/accelerants/radeon/monitor_detection.c

436

old_crtc2_gen_cntl = INREG(regs, RADEON_CRTC2_GEN_CNTL);

src/add-ons/accelerants/radeon/monitor_detection.c

441

OUTREG(regs, RADEON_CRTC2_GEN_CNTL,

src/add-ons/accelerants/radeon/monitor_detection.c

490

OUTREG(regs, RADEON_CRTC2_GEN_CNTL, old_crtc2_gen_cntl);

src/add-ons/accelerants/radeon/monitor_routing.c

34

values->crtc2_gen_cntl = INREG( regs, RADEON_CRTC2_GEN_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

426

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, values->crtc2_gen_cntl,

src/add-ons/accelerants/radeon/monitor_routing.c

521

crtc2_gen_cntl = INREG( regs, RADEON_CRTC2_GEN_CNTL );

src/add-ons/accelerants/radeon/monitor_routing.c

530

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl,

src/add-ons/accelerants/radeon_hd/bios.cpp

104

| Read32(OUT, RADEON_CRTC2_GEN_CNTL);