src/add-ons/accelerants/radeon/crtc.c

41

RADEON_CRTC2_DISP_DIS |

src/add-ons/accelerants/radeon/dpms.c

177

~(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS) );

src/add-ons/accelerants/radeon/dpms.c

180

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS),

src/add-ons/accelerants/radeon/dpms.c

181

~(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS) );

src/add-ons/accelerants/radeon/dpms.c

184

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS),

src/add-ons/accelerants/radeon/dpms.c

185

~(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS) );

src/add-ons/accelerants/radeon/dpms.c

188

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS),

src/add-ons/accelerants/radeon/dpms.c

189

~(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS) );

src/add-ons/accelerants/radeon/dpms.c

242

int mask = ~(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS);

src/add-ons/accelerants/radeon/dpms.c

249

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_HSYNC_DIS), mask );

src/add-ons/accelerants/radeon/dpms.c

252

OUTREGP( regs, RADEON_CRTC2_GEN_CNTL, (RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS), mask);

src/add-ons/accelerants/radeon/dpms.c

256

(RADEON_CRTC2_DISP_DIS | RADEON_CRTC2_VSYNC_DIS | RADEON_CRTC2_HSYNC_DIS), mask);

src/add-ons/accelerants/radeon/dpms.c

367

if( (tmp & RADEON_CRTC2_DISP_DIS) == 0 )