R92C_FPGA0_RFIFACESW
rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0));
rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000);
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(0), 0, 0x04000400);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1);
rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1),
rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(0));
rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(1));
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), 0x22204000);
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(0), 0, 0x04000400);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(0), vals->fpga0_rfifacesw0);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(1), vals->fpga0_rfifacesw1);
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACESW(idx),
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACESW(idx));
rtwn_bb_write(sc, R92C_FPGA0_RFIFACESW(idx), reg);