R92C_FPGA0_RFIFACEOE
rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1));
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(0), 0x400, 0);
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(1), 0x400, 0);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1);
rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(1));
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(0), 0x400, 0);
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(1), 0x400, 0);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(0), vals->fpga0_rfifaceoe0);
rtwn_bb_write(sc, R92C_FPGA0_RFIFACEOE(1), vals->fpga0_rfifaceoe1);
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
rtwn_bb_setbits(sc, R92C_FPGA0_RFIFACEOE(chain),
reg = rtwn_bb_read(sc, R92C_FPGA0_RFIFACEOE(0));