R92C_CR
rtwn_setbits_1(sc, R92C_CR, 0, R92C_CR_MACTXEN | R92C_CR_MACRXEN);
rtwn_setbits_1_shift(sc, R92C_CR, 0, R92C_CR_ENSWBCN, 1);
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSWBCN, 0, 1);
rtwn_write_2(sc, R92C_CR, 0);
rtwn_setbits_2(sc, R92C_CR, 0,
rtwn_write_1(sc, R92C_CR,
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
rtwn_write_1(sc, R92C_CR, 0);
rtwn_write_1(sc, R92C_CR,
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
rtwn_setbits_2(sc, R92C_CR, 0,
rtwn_setbits_2(sc, R92C_CR,
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0));
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
error = rtwn_write_1(sc, R92C_CR, 0);
rtwn_write_1(sc, R92C_CR,
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000));
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
error = rtwn_write_1(sc, R92C_CR, 0);
rtwn_write_1(sc, R92C_CR,
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);
RTWN_CHK(rtwn_write_2(sc, R92C_CR, 0x0000));
RTWN_CHK(rtwn_setbits_2(sc, R92C_CR, 0,
error = rtwn_write_1(sc, R92C_CR, 0);
rtwn_write_1(sc, R92C_CR,
rtwn_setbits_1_shift(sc, R92C_CR, R92C_CR_ENSEC, 0, 1);