R92C_APS_FSMCO
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
rtwn_setbits_1(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_PDN_EN);
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
rtwn_setbits_2(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_APDM_HPDN, 0);
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
rtwn_write_1(sc, R92C_APS_FSMCO + 3, 0);
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
rtwn_setbits_4(sc, R92C_APS_FSMCO, 0,
rtwn_setbits_2(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_ONMAC);
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
rtwn_write_2(sc, R92C_APS_FSMCO,
rtwn_write_1(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_PDN_EN);
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
RTWN_CHK(rtwn_write_2(sc, R92C_APS_FSMCO,
rtwn_write_2(sc, R92C_APS_FSMCO,
if (rtwn_read_1(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_PFM_ALDN)
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0xff,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_AFSM_HSUS,
if (rtwn_read_4(sc, R92C_APS_FSMCO) & R92C_APS_FSMCO_SUS_HOST)
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
if (!(rtwn_read_2(sc, R92C_APS_FSMCO) &
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0,
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, 0, R92C_APS_FSMCO_APFM_OFF,
if ((rtwn_read_2(sc, R92C_APS_FSMCO) &
rtwn_setbits_1_shift(sc, R92C_APS_FSMCO, R92C_APS_FSMCO_AFSM_PCIE,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,
RTWN_CHK(rtwn_setbits_1_shift(sc, R92C_APS_FSMCO,